– Xilinx announced the availability of three key connectivity IP cores critical to building flexible and cost-effective programmable 3G+/4G wireless base stations. Xilinx's Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE™ IP, JESD204 v1.1 LogiCORE IP, and CPRI v4.1 LogiCORE IP all support connectivity standards and will help developers address design challenges when creating new wireless equipment with greater system capacity.

With the growth of multiple wireless broadband data users and consumer demand, today's wireless infrastructure networks are insufficient. As mobile broadband users are expected to grow from 560 million in 2010 to 2.1 billion in 2015*, and average mobile broadband network connectivity speeds are expected to grow from 1Mbps in 2010 to 5Mbps in 2015, Xilinx's LogiCORE IP cores will help overcome greater system bandwidth requirements, enabling lower cost, flexibility, and a higher level of completeness.

Xilinx Connectivity IP Cores Enabling Next-Generation Wireless Infrastructure
The Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP is designed to the RapidIO Gen 2.2 specification from the RapidIO Trade Association and is the industry's first Gen 2.2 soft IP core supporting line rates up to 6.25G across 1x/2x/4x lane widths. Composed of a flexible and optimized Serial RapidIO physical layer core and logic (I/O) and transport layer cores, this IP core is supported by 7-series and Virtex®6 FPGAs and comes with a configurable fabric reference design that includes configurable buffer design, reference clock module, reset module, and flexibility in selecting functional blocks required by the application. The IP core also doubles data bandwidth in FPGA/CPU/DSP multi-processor farms, accommodating greater system data throughput by executing complex algorithms and signal processing functions in systems such as wireless infrastructure.

The CPRI v4.1 LogiCORE IP is designed to the CPRI (Common Public Radio Interface) standard specification v4.2 and is ideal for connectivity between a REC (Radio Equipment Controller) or baseband/channel card and one or more radio equipment (radio cards). Through distributed base stations and cloud-based RAN concepts that move the remote user closer for optimal capacity and service range, the CPRI protocol enables the operation of distributed base stations by remotely deploying radio heads. The IP core provides optimized implementation support for radio I/Q data, radio equipment management, and synchronization in one efficient protocol. Supported by 7-series FPGAs, Xilinx's CPRI v4.1 IP core doubles connectivity to remote radio heads up to 9.8G, improving system data capacity.

As data converter sample rates are rapidly increasing to support ever-growing system data throughput, Xilinx's JESD204B v.1.1 LogiCORE IP overcomes I/O constraints and PCB layout cost and complexity by replacing wide parallel interfaces to data converters with 1/2/4 high-speed serial interface links. The JESD204 v1.1 LogiCORE IP is the industry's first soft IP core designed to the JEDEC (Joint Electron Devices Engineering Council) JESD204B standard, which specifies the link protocol and serial data interface between data converters and logic devices. This IP core can be configured with JESD204B transmitter for interfacing to DAC devices or JESD204B for interfacing to ADC devices with the support of 7-series FPGAs.

Pricing and Availability
Serial RapidIO Gen 2 v1.2, CPRI v4.1, and JESD204B v1.1 LogiCORE IPs are available in Xilinx's ISE® Design Suite 13.3 and can be evaluated free of charge. (For more information, refer to the website www.xilinx.com/ise)