Xilinx and IBM Improve Connection Performance Between Accelerators and CPUs with PCI Express Gen4
Published2017.06.29 15:04Xilinx announced achievements regarding PCI Express® Gen4 capabilities.
Together with IBM, Xilinx has doubled the interconnect performance between accelerators and CPUs through PCI Express Gen4 compared to the widely used PCI Express Gen3 standard. Gen4 accelerates performance in data center applications such as artificial intelligence and data analytics by increasing the bandwidth between the CPU and accelerator to 16 Gbps per lane.
IBM and Xilinx demonstrated PCIe Gen4 capabilities for the first time in a programmable device by enabling Gen4 interoperability between Xilinx® 16nm UltraScale+™ devices and IBM POWER9 processors.
Bradley McCredie, IBM Vice President and Fellow, stated, "It is clear that future data center computing will be based on open standards," adding, "PCI Express leadership is one of the reasons why POWER architecture is used in modern data centers."
"We have faith in open standards," said Ivo Bolsens, CTO of Xilinx. "We are particularly pleased to be able to alleviate severe performance bottlenecks in accelerated computing, such as data center computing, through Xilinx's technological innovations."
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