-- With the expansion of the off-the-shelf and web-custom clock IC product portfolio
Achieves the industry's lowest power and highest density for the full range of PCIe applications --

January 30, 2012 – Silicon Laboratories Inc. (NASDAQ: SLAB), a leader in analog-intensive, high-performance mixed-signal ICs, announced today that it has secured the industry's most comprehensive range of clocking solutions capable of complying with demanding PCIe Gen 1/2/3 standards through the expansion of its PCI Express (PCIe) clock generator and clock buffer product families. Silicon Labs' expanded PCIe timing product family includes the off-the-shelf Si5214x clock generator and Si5315x clock buffer for PCIe applications where power and cost are critical, as well as the Si5335 web-custom clock generator/buffer for FPGA and SoC-based designs requiring various differential clock formats that comply with PCIe standards.

The PCIe interconnect standard is widely applied in numerous applications, including consumer electronics, blade servers, storage, embedded computing, IP gateways, and industrial systems. The PCIe interface is also supported on FPGA and SoC devices, enabling designers to utilize it as a versatile, high-performance solution for data transmission within systems. Silicon Labs provides a flexible set of clocking solutions that enable the use of PCIe designs to meet the requirements of various markets and applications by applying patented mixed-signal technology.

Mike Petrowski, General Manager of Timing Products at Silicon Labs, stated, “Silicon Labs is enabling customers to freely select the clocking solutions needed for their PCIe applications by applying a one-stop timing IC supplier model to the PCIe market. Through our expanded PCIe timing solution portfolio, developers can now use products that perfectly complement existing options to minimize power, increase signal integrity, and reduce costs, as well as industry-leading custom configurable clock generators and buffers for FPGA-based designs.”

Off-the-shelf PCIe clocking solutions
The Si5214x clock generator and Si5315x clock buffer product families consist of 2 to 9 output timing devices with industry-leading performance per watt. The power efficiency of the newly released PCIe clock generators and buffers is double that of third-party clocking solutions; their lower power consumption minimizes heat loss and reduces the need for additional cooling elements and power regulators. These devices can also meet PCIe jitter requirements with a margin of up to 50%, providing excellent system stability and improved bit error rates.

The Si5214x and Si5315x products, which further ease design complexity, reduce component count, BOM costs, board space, and power by integrating all external termination resistors using output buffer technology. In addition, this new clock generator and buffer product, the industry's smallest PCIe clocking device, is suitable for space-constrained applications.

The Si5214x and Si5315x product families provide programmable edge rate and skew control capabilities for individual outputs to overcome Electromagnetic Interference (EMI) and Radio Frequency Interference (RFI). Using the built-in I2C interface, developers can fine-tune signals and resolve integrity issues during operation without the need for additional components. Furthermore, these signal integrity tuning capabilities simplify EMI compliance issues, accelerating PCIe board design time-to-market.

Web-customized quad clock generator/buffer
The Si5335 clock generator/buffer IC is the industry's most easily customizable clocking solution for solving complex timing challenges in PCIe and FPGA-based applications. Shipped as custom pin-controlled Si5335 devices, they will be available without minimum order quantity starting two weeks from now via Silicon Labs' easy-to-use ClockBuilder™ web configuration utility ( www.silabs.com/Clockbuilder ). Up to four output frequencies ranging from 1 to 350 MHz can be configured in combination on the Si5335 output. In addition, up to three unique device configurations can be specified per part number, which allows the Si5335 to replace three separate clock generators or buffers and enables developers to reuse custom configurations of the Si5335 device in various designs.

The Si5335 clock generator/buffer IC simplifies PCIe and FPGA-based system designs with up to five user-assignable control pins and streamlines EMI compliance with its PCIe-compatible spread spectrum clocking options. Through Silicon Labs' patented MultiSynth fractional divider technology, the Si5335 device enables all-frequency synthesis at any output clock with sub-picosecond jitter. Furthermore, the Si5335 exceeds the performance requirements of PCIe, Ethernet, and mass storage industry standards. The Si5335's maximum jitter of 0.45 ps (rms) is more than twice as low as the PCIe 3.0 jitter requirement (1 ps).

The Si5335 simplifies multi-chip clocking challenges by supporting all combinations of differential formats, including single-ended forms such as LVPECL, LVDS, CML, and LVCMOS. By eliminating the need for multiple clock generators and/or buffers, the device supports combinations of four differential outputs or up to eight LVCMOS outputs. Based on this flexibility in output formats, designers can easily utilize power supply voltages and various output signal formats common to PCIe, FPGA, and SoC-based embedded systems.