Altera Demonstrates Industry's First Model-Based Floating-Point DSP Performance for FPGA

Altera's New High-Efficiency Floating-Point Design Flow Validated by BDTI, the Industry's Most Trusted Independent DSP Technology Analysis Organization

Hong Kong, September 15, 2011 — Altera Corporation (NASDAQ: ALTR) today demonstrated its new floating-point DSP design flow through FPGA, the industry's first model-based floating-point design tool that enables implementation of complex floating-point DSP algorithms on DSP.

Berkeley Design Technology, Inc. (BDTI) through independent analysis has validated high performance, efficiency, and the high performance, efficiency, and ease of use in the implementation of floating-point DSP design on Altera's Stratix® and Arria® FPGA product families. Altera's floating-point DSP design flow includes Altera's floating-point DSP compiler integrated into DSP Builder Advanced Blockset, the Quartus® II RTL tool chain, the ModelSim simulator, as well as MathWorks' MATLAB and Simulink tools that simplify the process of implementing DSP algorithms on FPGA. The floating-point design flow integrates algorithm modeling and simulation, RTL generation, synthesis, place-and-route, and design verification stages. This integration enables rapid development and design space exploration at both the algorithm and FPGA levels, ultimately reducing overall design effort.

Vince Hu, Vice President of Product and Corporate Marketing at Altera, stated, "Using Altera's high-level DSP model-based flow, designers can implement and verify floating-point algorithms more efficiently and rapidly than what is possible through traditional HDL-based design. Once the algorithm is modeled and debugged at a high level, the design can be easily synthesized and applied to any Altera FPGA."

Altera's new design flow is well-suited for difficult linear algebra problems that typically require the dynamic range provided by floating-point. BDTI benchmarked a parameterizable floating-point matrix inverse design. Matrix inversion is a representative processing operation used in various DSP applications including radar systems, MIMO wireless systems, and medical imaging.

In evaluating Altera's floating-point design flow, independent technology analysis company BDTI stated, "Rather than building a datapath composed of basic floating-point operators, the floating-point compiler generates a fused datapath that integrates basic operators into single functions or datapaths. This eliminates unnecessary redundancies that appear in traditional floating-point FPGA designs." BDTI concluded, "Through the fused datapath methodology, complex floating-point datapaths can be implemented to provide higher performance and efficiency than was previously possible."

The full BDTI FPGA Floating-Point DSP Design Flow Analysis Report can be found at www.altera.com/floatingpoint.