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Announcement of clock buffer providing ultra-low noise floor and additional jitter

Google 우선 소스Published2012.04.04 12:28

TI Korea (CEO Kent Jeon, www.ti.com/ww/kr ) April 4, 2012 – TI has expanded its high-performance clock buffer portfolio by launching two new general-purpose clock buffer families. The CDCLVC1310 LVCMOS clock buffer provides an industry-leading phase noise floor of -169 dBc/Hz in crystal mode. The LMK00101/05 complements the family with flexible output voltage level setting capabilities. The jitter characteristics of the LMK00301/04/06/08 differential end families are ultra-low at 51 fs (femtoseconds).

In response to modern communication systems that require strict system jitter budgets as data transfer speeds increase, these devices provide low jitter, skew, and built-in signal-level translators. These new product families support applications such as networking and data communications, medical imaging, test and measurement, and radar. (For data sheets and IBIS model downloads, free sample orders, and evaluation module applications, please refer to www.ti.com/universalbuffers-pr )

Features and advantages of CDCLVC1310, LMK00101/105
• Ultra-low system jitter performance (25fs) and superior noise floor characteristics in crystal mode support enhanced system communication link and signal-to-noise (SNR) performance.
• Universal input architecture (LVPECL, LVDS, HCSL, SSTL, LVCMOS) and built-in voltage level and signal translators reduce board space by 50%
• General-purpose I/O supply voltages (1.5V, 1.8V, 2.5V, 3.3V) simplify system design and reduce Bill of Material (BOM) costs by up to 50%

Features and advantages of LMK0030x (LMK00301/04/06/08)
• An additional 51fs RMS jitter at 156.25MHz (12kHz–20MHz) provides more than twice the flexibility of the closest competing devices, supporting enhanced system link performance.
• A general-purpose output architecture featuring built-in voltage levels and signal translators eliminates the need for interface logic and external components, saving over 50% of board space.
• Configurable output clock reduces customer R&D device evaluation costs by more than 50%

TI offers a vast portfolio of complementary devices capable of optimizing high-speed signal chains. Some devices that complement these clock buffers are as follows:
• Clock Generator: LMK03806, CDCM61001
• High-speed data converters: DAC3484, ADS4149, ADC12D1800RF product family
• DSP (Digital signal processor): TMS320C66x.

Supply timing and price
The following general-purpose clock buffers are currently in mass production and are being supplied through TI and its authorized distributors. In addition, you can check the pin, package size, and price per unit based on a quantity of 1,000 through the following table.

Price per unit based on 1,000 device pin packages
LMK00301 48 LLP $2.95
LMK00308 40 LLP $2.85
LMK00306 36 LLP $2.75
LMK00304 32 LLP $2.65
LMK00101 32 LLP $2.20
LMK00105 24 LLP $1.50
CDCLVC1310 32 QFN $2.35

In the second quarter of 2012, TI is scheduled to announce another fan-out buffer capable of distributing eight radiated differential-end clock outputs for low-power requirements.

More detailed information on TI's clock buffer solutions
• Order free samples, apply for EVM, download data sheets and IBIS models: www.ti.com/universalbuffers-pr
• Full Clock and Timing Portfolio: www.ti.com/clock-pr
• Questions and troubleshooting in the TI E2E™ Community Clock and Timer Forums:
http://e2e.ti.com/support/clocks/f/48.aspx
• Rapid search for TI's entire interface portfolio and download the latest selection guide:
www.ti.com/interface-pr
• Technical article on clock buffers or other signal chains and power supplies: www.ti.com/aaj-pr

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