Dual 16-bit 1.25GSPS DACs with integrated JESD204 serial inputs to simplify FPGA interfacing
June 19, 2012 – Analog Devices, Inc. ( www.analog.com , NASDAQ: ADI), an innovator in data conversion and signal processing technology and a data conversion market share leader for more than 47 years, today introduced the AD9128, the industry’s highest performance 16-bit, 1.25 GSPS transmit D/A converter (DAC) with integrated complex digital modulation functions and JESD204A compliant serial inputs. The AD9128’s high-speed serial interface dramatically simplifies and improves data connectivity between the DAC and FPGAs in a typical system implementation.
High-performance FPGAs are increasingly being used as processors in many data-driven wired and wireless communications, radar, avionics, and medical imaging applications. FPGAs have gained popularity due to their unique advantages, including easier system development, shorter time to market, high throughput, and in-flight programmability. However, for high-resolution data converter applications exceeding 1 GSPS, data transfer into and out of the FPGA has become a design bottleneck due to interface bit rate limitations, interconnect layout complexity, and parallel interface board space requirements. JESD204 was specifically developed to address these constraints, defining a robust, high-speed serial interface that can accommodate variable data rates in the multi-Gbps range. ADI is actively incorporating this standard into its high-speed data converter technology, and FPGA manufacturers are also actively integrating the protocol into their high-performance platforms.
The JESD204A-compliant AD9128 provides high sampling rate and dynamic range, multicarrier generation up to the Nyquist frequency, and includes features such as an on-chip 32-bit numerically-controlled oscillator (NCO) for flexible intermediate frequency (IF) use, and complex digital modulation, gain, and offset compensation. A 4-wire serial port is also provided for read-back and programming of many of the device’s internal parameters and functions. The AD9128 supports GSM, WCDMA, TD-SCDMA, CDMA2000, WiMAX, and LTE wireless communication standards.
AD9128 Dual 16-bit D/A Converter for Transmit Signal Chain IF Synthesis
• Supports IF bandwidth up to 500MHz with 1.25GSPS performance
• Excellent dynamic range:
80 dBc @ fDAC = 200 MSPS, fOUT = 50 MHz
72 dBc @ fDAC = 800 MSPS, fOUT = 70 MHz
80dBc @ fDAC = 200MSPS, fOUT = 50MHz
72dBc @ fDAC = 800MSPS, fOUT = 70MHz
• Single carrier W-CDMA ACLR = 82dBc @ 122.88MHz IF
• New 2×/4×/8× interpolator/composite modulator allows carrier placement anywhere within the DAC bandwidth
• Analog output: Adjustable from 8.7mA to 31.7mA, RL = 25Ω to 50Ω
• Four lanes of high-speed JESD204A serial links (each supporting 3.125 Gbps)
| Sample supply | Mass production announcement | Resolution (bits) | GROUND-COLOR: #98afc7; WIDTH: 54pt; BORDER-TOP: black 0.5pt solid; BORDER-RIGHT: black 0.5pt solid" class=xl63 width=72> Number of channelsSample rate (GSPS) | Price per 1,000 | Package | AD9128 | In supply | July | GHT: black 0.5pt solid" class=xl72 rowSpan=2 width=72> 162 | 1.25 | $34.50 | OR: transparent; WIDTH: 54pt; BORDER-TOP: black; BORDER-RIGHT: black 0.5pt solid" class=xl66 width=72> 56-lead
| LFCSP |
The analog output of the AD9128 high-speed D/A converter is optimized to interface seamlessly with analog quadrature modulators such as ADI's ADL537x F-MOD series, as well as the ADCLK914 clock/data buffer, which drives the AD9128 D/A converter with clock input jitter performance of 110 fs. Other complementary components include the ADRF6702 quadrature modulator and the ADRF6602 Rx mixer.
• View the AD9128 D/A converter product page, download the data sheet, and order samples: www.analog.com/AD9128
• The AD9128 DAC is available on a standard FMC evaluation board for direct connection to Xilinx FPGA development platforms. For more information, see the AD9128FMC link.
• Get support from ADI’s online technical support community, EngineerZone™: http://ez.analog.com/community/data_converters/high-speed_dacs















