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FEC IP core product aimed at reducing operating expenses (OpEx) and capital expenses (CapEx) for network operators

Google 우선 소스Published2012.06.20 17:32

Xilinx Korea (CEO An Heung-sik) June 20, 2012 – Xilinx announced its extended FEC (Forward Error Correction) IP (Intellectual Property) core products at the WMD and Next Generation Optical Networking 2012 conference being held at the Grimaldi Forum in Monaco. The product includes GFEC, eFEC, and high-gain FEC (xFEC) solutions used for error control in signal transmission and extending transmission distance. This reduces the number of regenerators (hops) along the route, thereby ultimately reducing operating expenses and capital expenses for network operators.

Xilinx designed the FEC IP core with a common interface to accelerate product development, minimize system-level integration time, and maximize design reuse to shorten time to market. The ultra-compact, high-performance FEC core includes GFEC IP cores for 2.5G, 10G, 40G, 100G applications, legacy 10G eFEC, and Xilinx's extended FEC (xFEC) IP core for 100G applications, which is particularly optimized for Xilinx FPGAs and occupies less silicon space than non-Xilinx IP cores, making it the smallest available FEC core currently. Additionally, Xilinx is working to add 400G GFEC with a target release in Q2 2013 for the latest applications. With partial reconfiguration, these IP cores optimized for Xilinx FPGAs enable customers to integrate multiple FEC standards across multiple interfaces while reducing product cost and power consumption and maximizing network interoperability.

Nick Possley, Senior Director of Wired Communications at Xilinx, stated, "As bandwidth demand increases and error and latency tolerances decrease, system designers are seeking new ways to expand available bandwidth while improving transmission quality." He added, "Xilinx has expanded its leading position in the OTN market by introducing extended FEC IP cores for 2.5G, 10G, 40G, 100G, and 400G applications to address this challenge. With the power/performance of the 7 series FPGA product family combined with the FEC portfolio, customers can now achieve higher data speeds and bandwidth while reducing system costs within the OTN application space."

With FEC, error control is maintained between the source (transmitter) sending redundant data signals and the destination (receiver) recognizing only apparently error-free data portions. Since FEC used in all OTN systems provides coding gain, users can transmit signals over greater distances by correcting errors that may occur as the signal-to-noise ratio decreases with distance, and can still achieve the same error rate at distant end receivers.

Different FEC schemes provide different levels of coding gain. The higher the coding gain, the greater the distance over which optical signals can be transmitted. For example, Xilinx's 100G extended FEC (xFEC) provides an industry-leading 9.4dB NECG at 6.7% OH. This extends 100G transmission distance and reduces 100G transmission output.

The coding gain provided by FEC is used for multiple functions, including extending system range by increasing maximum span length/span number. It is also useful for increasing the number of DWDM (dense wavelength division multiplexing) channels, which are limited by the output power of amplifiers used in one system. Additionally, coding gain reduces power per channel, increases the number of channels or relaxes specific link component parameters (such as initial output, eye mask, extinction ratio, noise figure, filter isolation), and reduces component costs.

Availability and Ordering Information
Xilinx OTU1, 2, 3, 4 (2.5G, 10G, 40G, 100G) GFEC IP cores comply with ITU G.709 standards and are available for purchase now, while 100G high-gain xFEC is scheduled for release in December 2012. Additionally, Xilinx plans to add EFEC standard implementations to meet customer needs.

Xilinx's FEC IP cores are competitively priced and require only a single project license, so royalties do not accrue repeatedly. To maximize all core functions in simulation and hardware, one license per core must be purchased. License purchase is available through the Optical Transport Network Solutions page. For information on pricing and availability of Xilinx FEC IP cores, please contact your local Xilinx distributor or FAE.

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