Xilinx Korea (Country Manager Heung-sik Ahn) July 3, 2012 – Xilinx announced a design solution utilizing integrated blocks for PCI Express® x8 Gen3 embedded in the Virtex®-7 FPGA and DDR3 external memory. This provides developers with all the functional blocks immediately applicable to PCI Express Gen3-based designs. With Xilinx® Integrated Blocks for the PCI Express Gen3 standard and support for an 1866 Mb/s high-speed memory interface on mid-speed devices, developers can design systems to meet the high system bandwidth requirements for communications, storage, and server applications.

The 1866Mb/s DDR3 solution delivers 40% higher performance compared to competitor memory solutions, providing maximum memory data speeds in mid-speed class devices. In addition, to enhance developer productivity, Xilinx has provided built-in features for single-root I/O virtualization and multi-function endpoints on the Virtex-7 XT device to meet the new requirements of data centers and cloud computing.

"By utilizing mid-speed devices, customers now have the various components necessary to implement high-performance PCI Express x8 Gen3-based designs at the lowest BOM costs," said Ketan Mehta, PCI Express Product Manager at Xilinx. "Xilinx provides Auto-Adaptive Decision Feedback Equalization (DFE), an industry-leading transceiver technology that automatically optimizes connected links, thereby maximizing productivity." “Development time is significantly reduced as the installation and use of high-speed serial transceivers supporting the PCI Express Gen3 standard are simplified,” he added.

The Virtex-7 XT and HT FPGAs are Xilinx's first-generation All Programmable devices that integrate hard IP cores satisfying the PCI Express Gen3 standard. Both the KINTEX™-7 and Virtex-7 FPGAs feature an 1866 Mb/s DDR3 external memory interface that maximizes PCI Express system throughput. Xilinx's PCI Express Gen3 video demonstrates that integrated blocks can be executed on the Virtex-7 X690T FPGA on existing PCI Express Gen3 systems.

For designs that do not use integrated blocks for the PCI Express Gen3 standard, soft IP core support is available through members of the Xilinx Alliance program, such as Northwest Logic and PLDA.