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PolarFire SoC Early Access Program Launched


As the importance of edge computing grows, RISC-V-based FPGAs and the ecosystem supporting them have been unveiled.

Microchip Technology announced on the 11th that it is launching an Early Access Program (EAP) for its PolarFire SoC FPGA.

By joining this EAP, you can start developing using Microchip's 'Libero SoC 12.3 FPGA Development Suite' and 'SoftConsole 6.2 IDE' for embedded developers. You can also debug your embedded applications using 'Renode,' a virtual model of a microprocessor subsystem.

The PolarFire SoC, which has 50% higher power efficiency than competing devices and requires no fan or heatsink, is an SoC FPGA equipped with a RISC-V CPU cluster and a deterministic L2 memory subsystem that supports Linux and real-time applications.

The PolarFire SoC has various debug features such as the AXI (Advanced eXtensible Interface) bus monitor, which enables instruction tracing and manual runtime configuration of the 'Ultra SoC', 50 breakpoints, an FPGA fabric monitor, and Microchip's built-in 2-channel logic analyzer, 'SmartDebug'.

In addition, the PolarFire SoC architecture is equipped with reliability and security features such as SEC-DED (Single Error Correction and Double Error Detection) for all memory, physical memory protection, DPA (Differential Power Analysis) Safe Crypto Core, defense-grade secure boot, and 128Kb flash boot memory.

Bruce Weyer, Vice President of Microchip’s FPGA Business Unit, stated, “By providing the industry’s first RISC-V-based SoC FPGA with the Mi-V ecosystem, Microchip and its Mi-V ecosystem partners have become leaders in innovation within the embedded environment,” adding, “Customers will now be able to add new capabilities for communications, defense, healthcare, and industrial automation to the network edge.”

Mi-V ecosystem partners supporting the PolarFire SoC include Wind River, Mentor Graphics, and WolfSSL, ExpressLogic, Veridify, Hex Five, and Free RTOS are included, along with development tools for the IAR system and AdaCore.