“Die to Wafer Hybrid Bonding (D2W Bonding) is a technology that has been in development for a long time, but scaling is just beginning.”

This is what Eric Bayne, Vice President of imec, said at SEMICON Korea 2023. He predicted that D2W hybrid bonding will be quite promising from the interconnect pitch below 10µm to the 2µm pitch.

The history of semiconductor scale-down is the history of 'high integration'. The success or failure was determined by how many semiconductor devices were integrated into the same area. Now that EUV technology has been used to achieve line width miniaturization, the physical limits of miniaturization have become clear.

Among these, attention is being focused on packaging as the RC delay of wiring in the BEOL (Back End of Line) process is being pointed out as the cause of performance degradation rather than the RC delay of the component.

The semiconductor industry has long been concerned with optimizing interconnection in packaging and has been striving for technological advancement. Today, interconnect technology is inevitably required to make I/Os more numerous, shorter, and more efficient in structures such as chiplets and 3D stacking, and related technology development is actively underway.

■ Hybrid Bonding, AMD-TSMC D2W Shockwave
Hybrid bonding, which has recently attracted much attention, has emerged as a next-generation technology due to the pitch limitations of microbumps. While wafer-to-wafer (W2W) hybrid bonding has already been applied to mass production in CMOS image sensors, D2W technology, which has not been applied to actual products due to its low technological maturity, has been applied to AMD products.

AMD released the Ryzen 7 5800X3D in April 2022. AMD's 3D V-Cache, which has been in development for several years, is a technology that realizes D2W through copper hybrid bonding, and the Ryzen 7 5800X3D is the first product to apply this technology. A 64MB cache die was stacked on top of the existing 32MB L3 cache to implement a total of 96MB L3 cache.

By increasing I/O density and reducing wiring length through copper interconnection between die and wafer, we achieved scale down in all areas including performance and power efficiency.

AMD Vice President Joseph Macri explained that 3D V-Cache has 200 times the interconnect density of 2D chiplets and 15 times the density of microbumps in 3D packaging, while improving energy efficiency by about 3 times.

Based on TSMC's 7nm process, 3D SoIC technology is applied, and the Ryzen 9 7950X3D, which will be released in February, is mass-produced with TSMC's 5nm FinFET process and has 128MB L3 cache stacked. AMD said that it can achieve a 9µm pitch through hybrid bonding in the 3D architecture. The current generation Zen3 architecture is known to have a TSV pitch of 17µm, and the next-generation architecture Zen4 is expected to reduce this pitch further.

Eric Bain, Vice President of imec, said, “In D2W, the direct method has a high risk of defects due to particles, so we will solve the particle problem through the collective method (Collective D2W).”

While the direct method has difficulties in particle management during die placement, the collective method is a proven technology that has advantages in die activation and cleaning equivalent to W2W hybrid bonding, and its advantages include oxide management and rework on the carrier. However, additional costs may arise for carrier preparation and cleaning, etc.

■ Besi, EVG, AMAT, Building a Hybrid Ecosystem

In the next-generation packaging market, equipment manufacturers are busy with hybrid bonding solutions. The industry is also not shying away from accelerating the roadmap through ecosystem creation and cooperation to seize new growth opportunities. Besi, a Dutch supplier of semiconductor packaging equipment, is working with Applied Materials (AMAT) to develop hybrid bonding equipment. The two companies will establish a Center of Excellence (COE) focused on next-generation chip-to-chip bonding technology, which will see the development of hybrid bonding solutions based on Besi’s die placement, interconnect, and assembly solutions and AMAT’s expertise across all processes including etching, planarization, and cleaning.

Besi has a portfolio in △Die Attach △Packaging △Plating and develops and produces equipment in △Die Bonding △Multi-Module Attachment △Soft Solder Die Bonding △Flip Chip, etc.

EV Group (EVG) is a company that provides equipment and process solutions for semiconductors, MEMS, compound semiconductors, and power devices, and has the technology required for the development of devices using nanotechnology. EVG has a product line including bonding, lithography, and measurement systems, including D2W, and has various bonding technologies such as hybrid bonding, Eutectic wafer bonding, and Com bond technology.

EVG is also working with AMAT to jointly develop W2W hybrid bonding. “3D joining and engineered materials are increasingly important in semiconductor innovation, and the demand for hybrid wafer bonding is very high,” said Thomas Ehrman, EVG Business Development Director.

“As semiconductor manufacturers increasingly embrace heterogeneous designs, Applied is working with partners like Besi and EVG to provide the capabilities needed to develop and deploy hybrid bonding technologies, including D2W and W2W,” said Vincent DiCaprio, managing director of AMAT Advanced Packaging Business Development.