KAIST has developed next-generation computing hardware that rapidly solves combinatorial optimization challenges using only standard CMOS semiconductor processes, and its application in various industries such as logistics, finance, and semiconductor circuit design is expected.

KAIST announced on the 22nd that a joint research team led by Professor Yang-Kyu Choi and Professor Sang-Hyun Kim of the Department of Electrical and Electronic Engineering recently implemented an oscillator-based ising machine hardware using only silicon CMOS, which is the mainstay of existing semiconductor processes.

By rapidly converging combinatorial optimization problems—which seek optimal solutions from a vast number of cases—into a physical synchronization process, it is expected to have broad industrial applications, such as logistics route optimization, financial portfolio construction, and semiconductor circuit design.

Combinatorial optimization is considered a difficult problem where computation time on conventional computers increases rapidly as the problem size grows.

The research team transformed this into an energy minimization form of the Ising model and focused on a structure that finds a solution by utilizing collective dynamics in which multiple oscillators exchange signals and align their phases.

In this case, the phase of the oscillator corresponds to the spin state, and the coupling between oscillators corresponds to the spin interaction.

Existing CMOS-based approaches have difficulty controlling frequency deviation and coupled circuitsThe complexity of the road network imposed limitations on large-scale integration.

The research team announced that they proposed a new structure in which both the oscillator and the coupler are composed of a single silicon transistor, enabling precise correction of frequency deviations using gate voltage and the implementation of multi-bit coupling capable of incorporating weights.

In the performance verification, the Max-Cut problem, a representative combinatorial optimization task, was solved.

Small-scale performance was verified using actual hardware, while 100-node scale performance was checked using semi-empirical simulations based on experimental data.

Max-Cut is a problem of dividing a network into two groups such that the sum of the connections (weights) between the groups is maximized, and it is used in various fields such as logistics, telecommunications, and semiconductor design.

Another significance of this achievement is that it utilized the standard CMOS process used in existing semiconductor factories without the need for special materials or separate processes.

It is evaluated that it has increased the potential for mass production and commercialization by lowering the burden of additional facility investment.

Professor Choi Yang-kyu stated, “This is a case where scalability and precision were secured simultaneously with a silicon-based single device,” mentioning the potential for application in industries requiring large-scale optimization.

KAIST doctoral student Sung-Yoon Yoon and Dr. Jun-Pyo Kim participated in the study as co-first authors, and the results were published in the international academic journal Science Advances.

The research was conducted with support from the National Research Foundation of Korea’s Next-Generation Intelligent Semiconductor Technology Development Project, the National Semiconductor Laboratory Support Core Technology Development Project, and the PIM Artificial Intelligence Semiconductor Core Technology Development Project.