Xilinx Korea (Country Manager Heung-sik Ahn) May 6, 2015 – Xilinx announced the release of Vivado® Design Suite 2015.1, which accelerates system verification. This marks a significant advancement in the productivity required for the development and deployment of all-programmable FPGAs and SoCs. This release includes Vivado Lab Edition, an accelerated Vivado simulator and third-party simulation flows, interactive Clock Domain Crossing (CDC) analysis, and advanced system performance analysis along with the Xilinx® Software Development Kit (SDK).

New Vivado Lab Edition

Vivado Lab Edition is a free, lightweight programming debug edition of the Vivado Design Suite. This Lab Edition includes the Vivado Device Programmer, Vivado Logic and Serial I/O Analyzer, as well as memory debug tools. It is also designed for use in lab environments where the full-featured Vivado Design Suite is not required. Since Vivado Lab Edition is 75% smaller than the full Vivado Design Edition, it significantly reduces lab installation time and system memory requirements. For design teams requiring remote debugging or programming via Ethernet, Vivado Design Suite 2015.1 provides a standalone hardware server. This is less than 1% the size of the full Vivado Design Edition.

Vivado Simulator and Third-Party Simulation Flow

Vivado Design Suite 2015.1 can reduce the number of LogiCORE™ IP compilations by more than double through advancements in the simulation flow. As a result, overall simulation performance is 20% faster than the previous release. This release includes fully integrated simulation flows from Alliance program members Aldec, Cadence Design Systems, Mentor Graphics, and Synopsys.

Dr. Stanley Hyduke, CEO of Aldec, stated, “Aldec is currently achieving full integration of Riviera-PRO and Active-HDL within the Vivado design suite using Xilinx’s Vivado Tcl store infrastructure,” adding, “This unique integration capability allows customers to enjoy even greater ease of use.”

Interactive CDC (Clock Domain Crossing) Analysis

Xilinx has expanded its advanced verification portfolio by providing interactive CDC analysis capabilities. This feature enables debugging of CDC issues from the early design stage and improves productivity by reducing costly in-system debug cycles. Combined with the interactive timing analysis and cross-probing capabilities of the Vivado Design Suite, this CDC analysis feature can shorten time-to-market through powerful timing analysis and debugging functionality.

Extending Xilinx SDK with advanced in-system performance analysis and verification

Xilinx has expanded its system performance and analysis toolbox for bare metal and Linux applications to accelerate the development of the Zynq®-7000 All Programmable SoC. Through the Xilinx SDK, embedded software developers can analyze the performance and bandwidth of SoC designs. This includes key performance indicators of the processor subsystem (PS), as well as bandwidth analysis between the PS, programmable logic (PL), and external memory. System modeling designs using the AXI traffic generator are provided for the Zynq-7000 All Programmable SoC ZC702 and ZC706 evaluation boards.

Usage period

Vivado Design Suite 2015.1 is now available and supports Xilinx 7 Series FPGAs, SoCs, and UltraScale™ devices. Vivado Design Suite 2015.1 can be downloaded from www.xilinx.com/download. You can explore the details of the new Vivado 2015.1 QuickTake videos and sign up for training. Additionally, you can increase productivity with UltraFast design techniques and target reference designs based on Vivado Design Suite.