Increase system efficiency and minimize power consumption and cost size

TI announced the launch of the AFE5818 and AFE5816 product families, which are 16-channel ultrasound analog front-ends (AFEs). Due to the nature of ultrasound examinations, devices must provide precise, advanced cardiac imaging and be portable, ranging from emergency patients to fetal examinations for pregnant women nearing childbirth. The newly released AFEs meet these requirements for portability and precision, ensuring image quality while minimizing power and system costs.

The product family can further simplify the drayout and reduce costs by providing multiple versions with or without demodulation blocks and interface options.

The AFE5818 and AFE5816 product families are the industry's first to offer 16 channels while optimizing the system level with a sampling AFE. Additionally, these two families provide low power consumption of 94mW and 52mW, respectively, which is a 33% improvement per channel. The AFE58JD18 and AFE58JD16 feature a 5Gbps JESD204B serial interface, reducing ultrasonic system data I/O routing by more than 80% compared to other data interface standards and providing a maximum data transfer rate of 6.4Gbps. This standard interface enables seamless connectivity with high-performance processors such as TI's 66AK2L06 multicore processor.

Integrated digital demodulator , providing high image quality

It includes a DTGC engine with 0.125dB resolution to reduce noise and power consumption. Unlike conventional analog time gain compensation, DTGC also reduces the need for external components.
The AFE58JD18 and AFE58JD16 provide low latency and high image quality by integrating an on-chip digital demodulator that regulates 16-channel data from RF to baseband frequencies, thereby reducing the load on the system processing engine.

TI’s ADS52J90 is a new 16-channel high-speed analog-to-digital converter (ADC) that complements the AFE5818 and AFE5816 families. It can be configured for up to 32 inputs, making it suitable for ultrasonic receiver designs requiring greater front-end design flexibility. Additionally, the ADC includes an on-chip digital demodulator that reduces processor and FPGA costs, as well as a low-voltage differential signaling (LVDS) or JESD204B serial interface that provides fast data transfer rates.