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ARM Announces New Bus Interconnect and Memory Controller Technology

Google 우선 소스Published2016.09.30 10:19
System IP for improving SoC performance across cloud environments

ARM has announced new bus interconnect and memory controller technologies that can meet the demands for scalability, performance, and efficiency in a wide range of applications, including 5G, data center infrastructure, high-performance computing (HPC), automotive, and industrial systems.

The newly announced ARM® CoreLink® CMN-600 Coherent Mesh Network interconnect and CoreLink DMC-620 DDR controller enable the development of advanced ARM-based SoCs that deliver unparalleled data processing capabilities and the lowest latency on the market.

“Cloud service providers need to be able to integrate more efficient compute power into their infrastructure to meet the demands of cloud-based business models,” said Monika Biddulph, general manager of ARM’s Systems and Software Group. “Based on the ARMv8-A architecture, CoreLink system IP seamlessly integrates heterogeneous compute and acceleration capabilities.” “This enables optimal computational density and workload optimization even within certain power and space constraints,” he said.



The 3rd generation CoreLink coherent backplane delivers optimal performance and efficiency anywhere in the network, from the terminal to the cloud, enabling an Intelligent Flexible Cloud.

Optimized for the latest ARM Cortex®-A processors, the CoreLink CMN-600 and CoreLink DMC-620 are the industry's only fully coherent backplane IP solutions supporting the ARMv8-A architecture. Featuring the ARM AMBA® 5 CHI interface, the industry standard for high-performance on-chip bus technology, designers and system architects can scale high-performance SoC designs from 1 to 128 Cortex-A CPUs (32 clusters).

The advanced ARM Socrates™ system IP tool accelerates SoC design by integrating ARM coherent backplane IP. CoreLink Creator's ARM intelligent solution automatically implements scalable, customizable mesh interconnect technology and generates RTL in minutes. The ARM Socrates DE enables rapid configuration and connection of IP blocks, enabling connectivity of AMBA-based IPs.

ARM Fast Models enable software development to begin before the chip is even built. Fast Models accurately expose the functionality of ARM IP, enabling programmers to develop software such as drivers, firmware, operating systems, and applications. ARM's ongoing collaboration with the open source community has enabled CoreLInk system IP to leverage open source drivers, accelerating software development times.
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