Link reconfiguration and change possible through partial reconstruction technology
FPGA size optimization, reconfigurability while maintaining connectivity

Xilinx announced the 2017.1 release of its Vivado® Design Suite HLx Edition.

This tool enables dynamic field updates and partial reconfiguration technology that increases system integration in a wide range of applications, including wired and wireless networking, test and measurement, aerospace and defense, automotive, and data centers.

Xilinx's Partial Reconfiguration technology allows designers to change functionality on the fly without having to reconfigure and re-establish links. With critical features enabled, it provides the ability to update applied system features, fix bugs, and migrate to new standards, increasing system upgradeability and reliability.



“Partial reconfiguration on Xilinx devices allows us to optimize FPGA size and maintain system connectivity while providing the flexibility to individually reconfigure multiple ports during design,” said Craig Palmer, senior engineering manager at Viavi Solutions.

Partial Reconfiguration technology enables dynamic configuration by replacing part of the design while leaving the rest running, without requiring downtime or impacting cost or development time.

“Partial reconfiguration of FPGAs is a key element of Keysight’s toolbox for creating next-generation test and measurement solutions,” said Tom Vandeplas, principal scientist at Keysight Laboratories, Keysight Technologies, Inc. “Partial reconfiguration enables us to address the ever-increasing demands for test system flexibility and complexity.”