| Silicon Labs Si539x Jitter Cleaner, Supports Fronthaul/Backhaul, Metro/Core, and Data Center Designs with a Larger Number of Ports

Silicon Labs announced on the 20th that it is adding a new optional product to its Si539x jitter attenuator family.

Silicon Labs Si539x

The new product fully integrates the reference, enhancing the reliability and performance of high-speed networking systems and simplifying the PCB layout.

The new Si539x jitter attenuator is designed to meet the demanding reference clock requirements of 100/200/400/600/800G designs.

It meets the jitter requirements of 56G PAM-4 SerDes used in SoCs, PHYs, FPGAs, and ASICs for Ethernet switches by more than 40% compared to the standard, and is also suitable for 112G SerDes designs.

The new Si539x jitter dampener incorporates a crystal that has been tested over a temperature range and preemptively blocks activity dips.

The Si539x guarantees quality through various reliability tests, including shock, vibration, temperature cycling, and crystal aging. The new device structure enables more consistent and reliable operation by reducing the crystal's sensitivity to temperature changes caused by the system fan.

A device structure integrating a reference increases resistance to acoustic emission (AE) compared to products using external crystals.

AE refers to noise radiation generated when temperature factors or external mechanical forces are applied during the PCB assembly stage, which can cause microcracks or plastic deformation in the PCB.

Unlike discrete crystals that suffer from significant frequency error problems due to AE, the package structure of the Si539x isolates and protects the crystal from AE noise, ensuring reliable operation and consistent frequency response characteristics over time.

Customers designing optical and Ethernet line cards with a large number of ports prioritize reducing overall board area.

By using a jitter attenuator with an integrated reference, developers can reduce the PCB footprint by more than 35%.

Additional advantages of reference integration include the elimination of the need to leave forbidden areas beneath the crystal, allowing for denser clock wiring connections around the device and further simplifying the PCB layout.

The Si539x device can generate up to 12 differential clock outputs for any frequency combination in the range of 100Hz to 1028MHz, eliminating the need for a separate standalone clock generator and clock buffer.

Thanks to this, clock-tree-on-a-chip clocking is possible, and concerns about additional jitter that can occur in discrete clock tree solutions can be eliminated.

James Wilson, General Manager of Timing Products at Silicon Labs, began by saying, “Network equipment suppliers are competing to supply products with faster speeds and larger capacities capable of handling 5G wireless traffic.”

He continued, “To move to these devices, higher-performance timing solutions are required for fronthaul/backhaul, metro/core, and data center applications,” and explained, “FPGAs and PHYs with embedded 56Gbps SerDes can implement larger capacity 100/200/400/600/800G optical and Ethernet line cards, but circuit board design becomes more complex and layout-related difficulties increase.”

"Silicon Labs stated, 'By integrating a reference inside the latest Si539x jitter attenuator, Silicon Labs enables the industry to easily transition to 100/200/400/600/800G designs with a greater number of ports and larger capacities.'"

The new Si539x jitter dampener is currently available as both a sample and a mass-production product.

Silicon Labs is offering various evaluation boards for the reference embedded or external Si539x for $299 each.

Using the evaluation board, users can quickly move from device configuration tasks to detailed performance evaluation, and by integrating with the ClockBuilder Pro tool, they can rapidly handle the development of custom settings and performance measurements.

For the price of the Si539x product, please contact your local sales office or official distributor. Si539x samples and evaluation boards can be ordered on the Silicon Labs website .