DRAM Becomes a Hindrance to CPUs Boosting AI Performance
| SMC 1000 8x25G, Allows 4x More DRAM Channels
| Connected to CPU via 8-bit OMI 25Gbps lanes

As computational demands for AI and machine learning workloads increase, conventional parallel-attached DRAM memory has emerged as a major obstacle for next-generation CPUs that require many memory channels to provide more memory bandwidth.

Microchip Technology announced on the 8th that it has entered the memory infrastructure market with the launch of its Serial Memory Controller (SMC).

The SMC 1000 8x25G enables CPUs and other compute-intensive SoCs to utilize four times more memory channels of parallel-attached DDR4 DRAM within the same package footprint.

Microchip's serial memory controller provides higher memory bandwidth and media independence to these computing-intensive platforms with extremely low latency.

As the number of processing cores within the CPU increased, the average memory bandwidth available to each processing core decreased, because it was impossible for CPU and SoC devices to expand the number of parallel DDR interfaces on a single chip to meet the need for a larger number of cores.

The SMC 1000 8x25G is an 8-bit open memory interfaceIt is connected to the CPU via 25Gbps lanes compliant with OMI and to the memory via a 72-bit DDR4 3200 interface. As a result, more memory channels were allowed and available memory bandwidth was increased, while the number of host CPUs required or the number of SoC pins per DDR4 memory channel was significantly reduced.

CPU or OMI-embedded SoCs can use combinations of various media types with different indicators in terms of price, power consumption, and performance without integrating a special memory controller for each type.

In contrast, current CPU and SoC memory interfaces are generally fixed to specific interface ratios for specific DDR interface protocols, such as DDR4.

The SMC 1000 8x25G is Microchip's first memory infrastructure product that enables a media-independent OMI interface.

Data center application workloads require OMI-based DDIMM memory products to provide the same high-performance bandwidth and low-latency results as current parallel-DDR-based memory products.

Microchip's SMC 1000 8x25G features a low-latency design with a latency of less than 4ns compared to existing integrated DDR controllers that include LRDIMM. As a result, OMI-based DDIMM products have nearly the same bandwidth and latency performance as LRDIMM products.

To support customers building OMI standard-compliant systems, the SMC 1000 provides ChipLink diagnostic tools along with built-in design and details.

The SMC 1000 8x25G is currently in sample production.