Advanced technology implementation algorithms are becoming more complex
Algorithm design described in HLS, HLL and implemented in RTL
Catapult HLS, Rapid RTL Generation Simplifies HW Development


Cutting-edge technologies such as computer vision, AI machine learning, and 5G are implemented with complex algorithms. When developing hardware to execute these algorithms, if each one is coded in hardware description languages (HDLs), such as VHDL and Verilog, the time taken is bound to be long due to the complexity and difficulty of the algorithms.

For example, when processing images with deep learning, many arithmetic operations and memory accesses are required. It is difficult to structure tens to hundreds of thousands of operations and memory accesses into hardware and code them manually.

High-level synthesis (HLS) is one way to solve this problem. It is to implement the algorithm design described in a high-level language (HLL) such as C, C++, or SystemC with a high level of abstraction in RTL (Register Transfer Level).

We met with Junseok Lee, a senior engineer at Mentor and Siemens Business, to ask him about how HLS is utilized in actual hardware development and about the 'Catapult HLS' platform that implements RTL hardware in high-level languages.


Q. What platform is Mentor's Catapult?
A. HLS is a method of synthesizing algorithm designs described in high-level abstraction languages such as C, C++, and SystemC into RTL hardware. And Catapult is a platform that implements RTL using high-level languages as input.


Q. How does Catapult implement RTL in a high-level language?
A. Not all designs in high-level languages can be directly converted to RTL using HLS. For example, multimedia video codecs such as H.264 or VP9 have open source reference codes. This code should not be directly input, but should be converted into a form that can be synthesized into hardware. If you want to get optimized RTL hardware, you need a C++ design that takes into account the hardware architecture.

Catapult analyzes the code when a design is input in a synthesizable high-level language. The designer applies hardware constraints such as operating frequency, clock, reset, and type of memory to the tool, and Catapult implements the RTL accordingly. During this process, architectural options such as pipelining and loop unrolling can be performed to meet latency and throughput design specifications.


Q. How does Catapult HLS reduce RTL generation time?
A. Catapult eliminates the need to describe every single operation in hardware description languages such as VHDL and Verilog, allowing designers to focus on the core functions of the algorithm they want to describe.

For example, in the case of a structure with very complex memory access, you can use HLS to declare an array of the required size, describe it as an operation, and apply the flow provided by Catapult for the rest to obtain hardware RTL. If you have to design all of this in a hardware description language, you have to decide on the method of accessing memory and its structure according to the design specifications, and design it accordingly, so it takes a long time to develop.

When we looked at the cases of domestic and international customers who introduced Catapult, it was found that the development period was shortened by an average of 2 to 3 times when using HLS compared to manual coding.

In addition, Catapult can use test benches written in C, C++, and SystemC as they are when verifying the generated RTL. Hardware simulation is possible with a test bench written in software. By using the verification flow of Catapult and conducting sufficient tests using various verification inputs, bug-free RTL can be generated.


Q. As AI becomes more widely used, the AI accelerator field is growing rapidly. I think Catapult will be useful in the relevant product development project.
A. In the AI accelerator ecosystem, algorithms are frequently modified, performance specifications may change, and integration into target platforms may change late in the design cycle. Additionally, design teams often find themselves having to compromise between power, performance, and area, which sometimes requires recoding hardware RTL.

If the design is changed due to a change in design criteria, the entire design and verification process must be restarted. This causes inevitable delays that cannot be tolerated in the production schedule and misses opportunities to explore and develop better hardware architectures.

Catapult provides a platform for designing, verifying, and connecting AI machine learning accelerators to systems using high-level synthesis flows. It supports the implementation and verification of hardware generated from designs described in high-level languages such as C++ into RTL optimized for power, process, and technology. It also provides math, DSP, and image processing libraries for rapid implementation.

The AI machine learning toolkit from Mentor provides real and proven accelerator-based reference designs such as pixel pipelining video processing and 2D convolution. It includes reconfigurable C++/SystemC IP source code, documentation, test benches, and scripts. This can be used to quickly advance AI projects.


Q. For what types of engineers would a catapult be useful?
A. Catapult is actually most useful to current RTL engineers. If you can create RTL in a high-level language, RTL engineers often worry that their jobs will disappear in the future. That is not the case in reality. Not only is the level of abstraction of the design language high, but the hardware structure analysis and understanding ability of RTL engineers with long-term RTL development experience increase the level of optimization of the results when utilizing HLS.

Let's assume that there is a design where loops are nested within a certain operation block, and operations that repeat reading and writing multiple memory accesses are performed. If the HLS design considers the hardware memory architecture, the design specifications can be easily satisfied with less memory. Otherwise, unnecessary memory will be used more, which will increase the overall cost for chip size. In addition, by describing it in a high-level language, the design period will be shortened, and the time required for verification will be greatly increased, enabling a more complete RTL hardware design.

It is also useful for software engineers. Software engineers have much more freedom in implementing core functions and can proceed with designs with a more flexible structure. They can respond quickly even if design changes occur in the middle of the development schedule. Engineers with some hardware knowledge can also implement hardware-side optimization to a considerable degree.

There are many developers who have good algorithms but cannot do anything but stay with software because they do not know hardware RTL. If these people utilize Catapult, they can easily generate hardware RTL for the software they are developing and conduct verification perfectly.

Software algorithm companies that had to outsource RTL development will be able to handle hardware directly and secure competitiveness in this regard. Catapult is a great help to both software and hardware engineers.