Korea's first 12-inch semiconductor testbed officially launched.
Building infrastructure capable of manufacturing 40nm patterned wafers
Support for future 20nm wafer manufacturing and component testing


Materials and components for semiconductor production are key items that raised awareness about the need for self-sufficiency in materials, components, and equipment (SME) technology in Korea following Japan's export restrictions in July 2019. Even before Japan's export restrictions, domestic semiconductor SME companies faced significant challenges due to the lack of 12-inch test beds comparable to the production environments of large corporations.

On the 17th, the Ministry of Science and ICT officially launched the service of the 12-inch semiconductor test bed built at the Nano Comprehensive Technology Institute (NCTI).

The material uniformity, defect, and other quality assessments required by semiconductor giants like Samsung Electronics and SK Hynix on 12-inch wafers were impossible in Korea. Consequently, most small and medium-sized enterprises (SMEs) were forced to either spend significant time and money on overseas test beds or settle for basic assessments using Jonggiwon's 8-inch equipment.

To address these issues, the Ministry of Science and ICT designated Jonggiwon as the operator of the 12-inch semiconductor small and medium-sized equipment test bed in August 2019, and invested a total of 45 billion won in national funds to build a clean room and 10 pieces of core equipment, and to promote equipment stabilization work, thereby launching official service. Semiconductor small and medium-sized enterprises can utilize this service to receive support for material performance testing.

Lee Jo-won, the president of Jonggiwon, said, “The current 12-inch test bed is an infrastructure capable of manufacturing 40nm patterned wafers, and we plan to intensively support the development of core semiconductor materials and equipment, such as photoresists,” and “In the future, we plan to promote the construction of additional equipment and the development of process technology that can support the manufacturing of 20nm-level patterned wafers and component testing.”