For edge computing system hardware acceleration
Microchip PolarFire FPGA products even more
Improved development convenience by making it easy to use


With the increase in high-performance, low-power edge computing applications, demand for FPGAs has risen, as they offer the benefits of accelerated power efficiency, flexibility, and shorter time-to-market. However, most edge computing, computer vision, and industrial control algorithms are developed primarily in C++ by developers with little to no knowledge of FPGA hardware.

On the 2nd, Microchip Technology added SmartHLS to its PolarFire FPGA family, a High Level Synthesis (HLS) design workflow that significantly improves productivity and design ease by directly converting C++ algorithms into FPGA-optimized Register Transfer Level (RTL) code to support this important development community.

Bruce Weyer, Vice President of Microchip’s FPGA Business Unit, said, “SmartHLS enhances the Libero® SoC design tool suite while helping the diverse algorithm developer community take advantage of Microchip’s mid-range PolarFire and PolarFire SoC platforms without FPGA hardware expertise.”

He added, “Using this tool together with the Microchip VectorBlox™ Neural Network SDK (Software Development Kit) can increase productivity when developing cutting-edge solutions using C/C++ based algorithms for applications such as embedded vision, machine learning, motor control, and industrial automation that use FPGA accelerators.”

Open Source EThe SmartHLS design suite, based on the ClipSe integrated development environment, uses C++ software code to generate HDL IP components necessary for integration into Microchip's Libero SmartDesign projects. Developers can represent hardware behavior at a higher level of abstraction than when using existing FPGA RTL tools.

The SmartHLS Design Suite reduces development time and increases productivity through multithreading APIs. Multithreading APIs execute hardware instructions concurrently and simplify complex hardware parallel representations compared to other HLS products.

SmartHLS tools, which require up to 10 times fewer lines of code than equivalent RTL designs, simplify the process of reading, understanding, testing, and debugging the final code. They streamline the exploration of hardware microarchitecture design trade-offs and enable developers to use PolarFire FPGAs and FPGA SoCs for existing C++ software implementations.

Developers can begin development using the SmartHLS v.2021.2 tool available on the Microchip website. This tool is included in the recently released Libero SoC V2021.2 design suite and can be used as standalone software.