The increasing demand for bandwidth and security in network infrastructure is driven by the rise in hybrid operations and the geographical distribution of networks. As a result, borderless networking is becoming a redefined trend.

According to the 650 Group, the total port bandwidth of 400G (gigabits per second) and 800G, driven by AI/ML applications, is projected to grow by more than 50% annually. This rapid growth is extending the trend of transitioning to 112G PAM4 connectivity beyond cloud data centers and telecommunications service provider switches and routers to enterprise Ethernet switching platforms.

Microchip Technology (hereinafter Microchip) announced on the 20th that it has launched a new META-DX2 Ethernet PHY portfolio featuring the new META-DX2+ PHY to respond to these market changes.

It was explained that this new product family is a solution integrating line-speed end-to-end encryption and port aggregation at 1.6T (terabits per second), enabling the transition to 112G PAM4 connectivity while maintaining the smallest footprint in enterprise Ethernet switches, security devices, cloud interconnect routers, and optical transmission systems.

Babak Samimi, Vice President of Communications at Microchip, stated, “Microchip is committed to supporting the market transition to connectivity with 112G PAM4 connections powered by the META-DX retimer and PHY portfolio through the introduction of these four new META-DX2+ Ethernet PHYs,” adding, “Together with the META-DX2L retimer, we provide a complete chipset that meets all connectivity requirements, ranging from retiring and gearboxing to advanced PHY functions.”

He said, “Because it provides footprint compatibility in both hardware and software, customers can leverage the architectural design across enterprise, data center, and service provider switching and routing systems.” “For advanced features such as end-to-end security and multi-speed port aggregation, you pay for what you use, and the precision timestamp feature is available via a software subscription,” he said.

Microchip emphasized that the configurable 1.6T data path architecture of the META-DX2+ leverages unique ShiftIO capabilities to achieve more than double the performance of competitors in total gearbox capacity and hitless 2:1 protection switch multiplexer (mux) mode. The flexible XpandIO port aggregation feature can optimize router/switch port utilization when supporting low-speed traffic, and this device also includes IEEE 1588 Class C/D PTP (Precision Time Protocol) support for accurate nanosecond timestamps required for 5G and enterprise business critical services.

Microchip stated that it offers an advanced PHY portfolio with footprint-compatible retimer and encryption options, enabling developers to extend designs with added MACsec and IPsec based on common board designs and SDKs (Software Development Kits).

Key features of the META-DX2+ include: dual 800 GbE, quad 400 GbE, and 16x 100/50/25/10/1 GbE MAC/PHY; an integrated 1.6T MACsec/IPsec engine that reduces the encryption burden on packet processors, allowing for easier system expansion to higher bandwidths through end-to-end security; board savings of over 20% compared to competing solutions requiring two devices when providing the same 1.6T gearbox and hitless 2:1 multiplexer mode; and XpandIO, which supports port aggregation for low-speed Ethernet clients through high-speed Ethernet interfaces optimized for enterprise platforms.

Alan Weckel, founder and technology analyst at 650 Group LLC, added, “As the industry transitions to the 112G PAM4 serial ecosystem for high-density routers and switches, the importance of line-speed encryption and the efficient use of port capacity is growing.”