Innovation in high-k materials is essential. New materials must be developed to address the resistance issues associated with shrinking contact sizes.

These are the words of SK Hynix CEO Kwak No-jeong, speaking on the topic of “Beyond the Limits of Memory Technology” at the 2022 Semiconductor Expo keynote event hosted by the Semiconductor Industry Association on the 5th.

CEO Kwak predicted that data usage has increased sharply since the proliferation of smartphones, and that cars will begin generating 40 terabytes (TB) of data per hour as they become increasingly equipped with autonomous driving features, communications, and electronic components. Accordingly, he predicted that the connected mobility market, encompassing advertising, insurance, and finance, will grow to over 10 trillion won annually by 2030.

Semiconductor technology is what enables processing this exploding data and driving market growth in related industries. The need for innovation in memory technology has long demanded a similar direction. The three key characteristics are △large capacity △high speed △low power.

Experts agree that while DRAM has begun mass production at the 10nm level through continuous scaling down, the limits of process miniaturization have been reached. CEO Kwak also predicted significant resistance to scaling down at the 10nm level due to factors such as reduced fin spacing and increased contact resistance due to smaller contact sizes, stating, "High NA EUV will absolutely be necessary for patterning."
He emphasized that innovation in "high-k materials" is necessary, particularly considering the capacitance issue of cell capacitors. He also added that new materials must be developed to address resistance issues resulting from shrinking contact sizes.

SK Hynix is researching and developing a new platform as a new scaling alternative. CEO Kwak stated, "We are considering applying 3D stacking technology to DRAM, similar to NAND flash." It is already known that Samsung Electronics and Micron of the United States are researching and developing 3D DRAM for next-generation products.

NAND flash technology has recently succeeded in developing 238-layer NAND flash through stacking technology, but CEO Kwak expressed concern, saying, “I am concerned about whether it will be possible to go beyond 400 layers.”

While increasing the number of NAND layers is necessary, the absolute height needs to be reduced. This necessitates the development of technologies to reduce oxide film thickness. Furthermore, as the number of layers increases, future challenges remain, such as how many NAND flashes after single-stack stacking (double-stack, triple-stack, etc.) should be connected to increase the number of layers, and how to reduce the associated costs.

CEO Kwak predicted that in order to improve the number of bits per unit area of NAND, “Currently, mass production of TLC (Triple Level Cell) is the main focus, but in the future, the trend will change to QLC (Quad Level Cell) and even PLC (Penta Level Cell).”

NAND flash is expanding its storage capacity through lateral scaling, which will require improved WL filling and low-resistance WL materials. CEO Kwak added, "Wafer bonding will be applied in the future."

Meanwhile, Semiconductor Expo 2022, featuring domestic and international semiconductor companies such as Samsung Electronics and SK Hynix, opened on the 5th and is currently underway at COEX in Samseong-dong, Seoul, for three days. This event, which showcases solutions for strengthening the semiconductor ecosystem and various semiconductor technologies, materials, components, and equipment, boasts 235 companies and 800 booths, making it the largest event ever and attracting significant attention.

(Reporter Kwon Shin-hyeok)