Release of Multiservice Line Card Adaptive Clock Converter Supporting a Wide Range of Wired Communication Applications
AD9557 and AD9558, synchronous Ethernet and
Wired communication such as SONET/SDH optical networks
Perform frequency conversion in the application
October 19, 2011 -- Analog Devices (www.analog.com), a global leader in high-performance semiconductors and a leader in the global data converter market, today introduced two fully programmable jitter-attenuated clock converter ICs that perform frequency conversion in a wide range of wired communication applications, such as synchronous Ethernet and SONET/SDH optical networks, where low jitter, fast time-to-market, and cost-effectiveness are required.
The AD9557 dual-input multiservice line card adaptive clock converter and the AD9558 quad-input multiservice line card adaptive clock converter convert input frequencies from 12 kHz to 20 MHz to output frequencies in the 2 kHz to 1.25 GHz range with only a total jitter of less than 400 fs RMS. These new clock converters offer superior performance compared to existing PLL designs that require the addition of expensive voltage-controlled crystal oscillators (VCXOs).
Thanks to the programming capabilities built into the AD9557 and AD9558 clock converters, network line card designers can use the same components in various different board designs, which not only reduces the number of required components but also lowers overall system costs. This includes synchronization for various high-performance applications such as data communications, next-generation wired networking applications, electronic communications, test and instrumentation, high-speed data acquisition, and wireless base station controllers.
The AD9557 and AD9558 clock converters integrate a frequency-agile VCO with low phase noise and excellent frequency tracking speed, a loop filter, and dynamic adaptive clock support. Additionally, adaptive clocking allows changing the ratio of the DPLL divider while maintaining the locked state of the digital PLL (DPLL). This feature eliminates the hassle of having to unlock the PLL loop and reprogram it to low steps of 0.1 ppb or less to fine-tune the output frequency within a range of ±100 ppm relative to the output nominal frequency.
These adaptive clock functions are used in applications such as SDH-OTN mapping/remapping and asynchronous mapping/remapping. The programmable DPLL of this adaptive clock converter supports loop bandwidths from 0.1 Hz to 5 kHz and features three distinct programming modes, offering excellent ease of use and flexibility. The two newly announced devices have pre-configured pins or soft pins to support widely used SONET/SDH, Ethernet, synchronous Ethernet, and Fibre Channel frequencies, and Serial Port Interface (SPI) and I2C ports are also available to program custom input-to-output frequency conversion.
Available in 6mm x 6mm and 9mm x 9mm sizes, the AD9557 and AD9558 clock converters provide economical and compact frequency-variable clocks for line card designers. The AD9557 features two reference inputs (single-ended or differential) and two pairs of clock outputs. Each output pair can be configured as a single differential LVDS/HSTL output or two single-ended CMOS outputs. The AD9558 also has the same specifications, but differs in that it has 4 reference inputs and 6 pairs of clock outputs.
Key specifications of AD9557 and AD9558 adaptive clock converters
• GR-1244 Stratum 3 stability support in Holdover mode
• Smooth reference switchover implementation with minimal disturbance in the output phase
• Telcordia GR-253 Jitter Generation, Transmission, and Tolerance Support from SONET/SDH to OC-192 Systems
• ITU-T G.8262 Synchronous Ethernet Slave Clock Support
• Supports ITU-T G.823, G.824, G.825, and G.8261
Complementary products
The AD9557 and AD9558 clock converters are suitable for use with the asynchronous AD9577 clock generator of dual PLLs, which provides the core elements of a clock tree for various applications. The AD9577 is an economical asynchronous clock solution that can be used in place of an oscillator to generate local clocks for processors, FPGAs, or PHYs in SONET/SDH, synchronous Ethernet applications, Ethernet enterprise switches, core/edge router fabric cards and line cards, Packet Transport Network (PTN), and Fibre Channel applications.















