Altera today announced its next-generation high-end PLD family, Stratix 10 FPGAs and SoCs, which deliver dramatic improvements in performance, integration, density, and security.

“HyperFlex is the greatest FPGA architecture innovation in the past decade,” said Patrick Dorsey, senior director of product marketing at Altera.

Stratix 10 FPGAs and SoCs deliver performance levels that the industry has never imagined possible before, enabling customers to design and innovate in ways never before possible with FPGAs, and meet the demanding needs of next-generation communications, data centers, IoT infrastructure, defense and high-performance computing systems.

Stratix 10 FPGAs and SoCs are Altera’s first products based on Intel’s 14nm Tri-Gate process, and feature Altera’s innovative HyperFlex FPGA fabric architecture, delivering core performance that is superior to previous-generation FPGAs.It has doubled the processing power while reducing power consumption by 70%, further strengthening Altera's leadership position as the only supplier of high-end SoC FPGAs.

HyperFlex Architecture: Registers Everywhere!

Stratix 10 FPGAs and SoCs are the first Altera devices to feature the new HyperFlex architecture, which eliminates critical path and routing delays by introducing registers into all interconnect routing areas of the core, thereby doubling core logic performance.

HyperFlex architecture solves the wiring delay problems of traditional architectures.

"Until now, routing delay has been the bottleneck that has limited the performance of FPGAs," said Patrick Dorsey.

HyperFlex architecture solves these wiring problems. That is, by adding a large number of hyper-registers, equivalent to 10 times the number of adaptive logic modules (ALMs), to every wiring area through the concept of 'Registers Everywhere', it enables excellent optimization functions such as Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization, thereby doubling the speed.

The addition of numerous hyper-registers enables powerful optimization capabilities.

"HyperFlex not only doubles speed by adding hyper-registers to the wiring, but also reduces board area by 30 percent due to a smaller bus size. It also reduces the required logic area, enabling high-performance designs to operate at up to 70 percent lower power. For example, in the case of Stratix 10, the same performance can be achieved with half the bus width of Stratix V, so the power required is also significantly reduced by 40% to 70%."

Hyperpipelining using hyper registers provides 2x speedup

These advantages make Stratix 10 an ideal solution for data centers where power consumption is emerging as a major challenge.

“Data centers are a new area where FPGAs are starting to be used, and with the Stratix 10, we can add hard floating-point DSPs to deliver speeds of up to 10 teraflops, replacing ASICs or GPUs in the data center,” said Patrick Dorsey.

“Of course, Stratix 10 will also see increasing use in other areas such as wireless, military, IoT infrastructure, and high-end broadcast systems,” he added.

Altera is eyeing data centers as a new application area for FPGAs.

Scalability and Flexibility Provided by Heterogeneous 3D SiP Technology

The Stratix 10 FPGA and SoC family leverages heterogeneous 3D SiP integration technology to efficiently and cost-effectively integrate high-density monolithic FPGA core fabric with other advanced components, enhancing scalability and flexibility.

What makes this possible is Intel’s patented Embedded Multi-die Interconnect Bridge (EMIB) technology, which achieves higher performance, reduced complexity, lower cost, and improved signal integrity over interposer-based techniques.

Future FPGA products will need to support transceivers at a variety of data rates, new modulation schemes, as well as rapidly evolving standards and diverse protocols.

However, since these standards have not been established yet, hard IPs cannot be created. Altera's heterogeneous 3D SiP technology enables it to rapidly deliver a variety of Stratix 10 device product versions to meet rapidly changing market demands.

“For example, while the first products in the Stratix 10 family today leverage this EMIB technology to integrate high-speed serial transceiver and protocol tiles into the monolithic core logic, future products could also integrate a variety of tiles that provide capabilities such as higher transceiver speeds (56 Gbps), multiport Ethernet, emerging communications standards such as PCIe Gen 4, new modulation formats (PAM-4), analog or high-bandwidth memory,” explained Patrick Dorsey.

Another power saving solution, Enpirion PowerSoC

"Altera is no longer just an FPGA company, it's also a power management company," said Patrick Dosey.

Altera's Enpirion PowerSoC power modules for Stratix 10 FPGAs and SoCs meet stringent performance and power requirements, achieving the highest efficiency while providing the smallest footprint.

"For example, Altera's Enpirion EM1130 PowerSoC supports the SmartVoltage I, which Intel uses in all of its programs.By introducing D(SmartVID) technology to Stratix 10, dynamic power consumption can be reduced by 20-25% depending on the application."

Maximize design protection with comprehensive security integration

Altera has worked with partners including Intrinsic-ID to achieve world-class levels of security, making Stratix 10 FPGAs and SoCs ideal for defense, cloud security, IoT infrastructure, and other applications where multilayered security and isolated IP protection are critical.

A key element that makes Stratix 10 FPGAs and SoCs the industry’s most comprehensive set of integrated security features and high-performance FPGAs is the innovative Secure Design Manager (SDM), which enables users to define and build customized, multi-layered security solutions.

SDM provides security features such as sector-based authentication and encryption, multi-factor authentication (MFA), and physically unclonable function (PUF) technology that makes physical cloning impossible. "For example, in the case of PUF, each device has a unique key determined in the process, so cloning itself is impossible," added Patrick Dosey.

A comprehensive design environment optimized for HyperFlex

Altera's comprehensive design environment provides a Hyper-Aware design flow optimized for HyperFlex to improve design productivity, accelerate time to market by reducing compile times and design iterations.

The new Spectra-Q engine introduced in Altera's Quartus II design software maximizes the performance, power, and area benefits of the HyperFlex architecture, enabling developers using Stratix 10 FPGAs and SoCs to improve design productivity and accelerate time to market.

Quartus II software reduces compile times by up to 8x and adds new features such as multiple design entry methods, drop-in IP integration, OpenCL support, and a high-level design flow. Developers can immediately begin development of Stratix 10 designs using the Fast Forward Compile performance evaluation tool.

Engineering samples of Stratix 10 FPGAs and SoCs are expected to be available in fall 2015. Embedded software developers can accelerate their Stratix 10 SoC embedded software development efforts by leveraging the SoC virtual platform available from Mentor Graphics. For more information on Stratix 10 FPGA and SoC products, contact your local Altera sales office or visit www.altera.com/stratix10.