Proactively Providing Security Platform Suitable for Long-Term Operating Infrastructure

AI Significantly Lowers FPGA Barriers to Entry, Productivity Up 10x ↑

As security enhancement in preparation for the quantum computing era and AI-based design automation have emerged as critical challenges for the semiconductor industry, Lattice Semiconductor is simultaneously introducing a next-generation security FPGA supporting post-quantum cryptography (PQC) and generative AI-based design software, tackling two strategic axes: 'security' and 'development productivity.' The strategy is to evolve FPGA from a simple programmable semiconductor into a Root of Trust platform for future infrastructure.

Lattice Semiconductor held an online press briefing on the 15th and announced a new security control FPGA product family 'Mach-N2' and an AI-based FPGA development tool 'Lattice Prompt'.

The focus of this announcement is aimed at simultaneously enhancing security and development efficiency in increasingly complex data center and network infrastructure environments.

Lee Ki-hoon, Director of Lattice Semiconductor, who led the presentation, stated, "In a situation where cyber attacks are expanding to data centers, telecommunications equipment, and edge devices, we will proactively provide a security platform suitable for long-term operating infrastructure."

The newly unveiled Mach-N2 was designed based on Lattice's compact FPGA platform, Nexus 2.

It supports up to 220K system logic cells and provides high-speed interfaces including PCIe 4.0, 10GbE, and SERDES up to 16Gbps.

Additionally, it supports performance up to 350MHz and focuses on implementing real-time control and security functions required in data centers and telecommunications infrastructure.

In particular, Director Lee Ki-hoon identified post-quantum cryptography technology as the greatest differentiator of Mach-N2.

The product complies with CNSA 2.0, the next-generation encryption standard of the U.S. National Security Agency (NSA), and supports ML-DSA, LMS, XMSS-based signatures and ML-KEM key exchange functions. Currently, in the long-term operating infrastructure market, transitioning to a security system in preparation for the emergence of quantum computers has emerged as an important task, and Lattice's strategy is to address this at the FPGA level.

Another axis of security enhancement is the integrated flash architecture.

Mach-N2 integrates non-volatile flash inside the FPGA, blocking physical access to external flash memory itself.

Additionally, it can store up to three configuration images, enabling immediate recovery to a backup or golden image in case of primary image corruption.

Director Lee Ki-hoon explained that this makes it possible to secure both security and system availability simultaneously.

Lattice also newly applied an Anti-Tamper function that detects voltage and temperature anomalies.

When the FPGA detects abnormal power fluctuations or temperature changes, it sends an interrupt to the user design area, and customers can directly define response methods such as system shutdown or recovery.

Through this, physical attacks or equipment tampering attempts can be detected more effectively.

Additionally, Mach-N2 achieves boot times within 30ms based on 220K logic cells utilizing the integrated flash architecture.

Director Lee Ki-hoon emphasized that this is approximately 10 times faster compared to competing products that generally require boot times exceeding 200ms.

Since secure boot and fault recovery times are important in servers and network equipment, this is evaluated as a key competitive advantage.

Lattice has already supplied samples to some customers in the computing and telecommunications fields and is pursuing market entry in next-generation server infrastructure including hyperscale data centers.

Director Lee Ki-hoon did not disclose a specific mass production timeline but stated that the product was developed reflecting customer requirements and implementation in various customer projects has already begun.

Lattice Prompt, unveiled together on that day, drew attention as an AI-based design tool that could significantly change FPGA development methods.

When developers input requirements in natural language, the solution automates major development processes from FPGA project creation to RTL code writing, compilation, timing optimization, simulation, and bitstream generation.

Lattice Prompt integrates with various AI development environments such as Claude Code, Cursor, and Visual Studio Code and supports the open-source MCP (Model Context Protocol).

Users can leverage their preferred AI agent while combining Lattice's design tool Lattice Radiant with the knowledge base to obtain more accurate design results.

Director Lee Ki-hoon stated that pre-validation results showed FPGA design productivity improved by over 10 times.

Development work that previously took several months has been confirmed to be shortened to several days or tens of hours, and software developers without FPGA development experience were able to convert Python or C code into RTL code for FPGA use, he explained.

For FPGA experts, improvements in timing optimization and reduced iterative design work are expected.

Director Lee Ki-hoon expressed expectations, stating, "As AI significantly lowers the barriers to entry in the FPGA design process, it will provide an environment where engineers can focus on innovative system design rather than repetitive tasks."