Xilinx Korea (CEO Heung-sik Ahn) August 13, 2015 – Xilinx, Inc. (NASDAQ: XLNX) today announced the availability of a Low-Density Parity-Check (LDPC) error correction IP core device, enabling next-generation flash-based applications for the cloud and data center storage markets. As NAND flash continues to evolve into 3D NAND technology, LDPC error correction has become a critical capability for meeting the stringent reliability and endurance requirements of today’s storage solutions. Featuring best-in-class code performance approaching the Shannon limit, Xilinx’s LDPC IP solution provides extremely low error floors and supports both hard and soft decision decoding. The architecture is scalable to support a variety of next-generation non-volatile memories and delivers high data throughput and low latency for demanding storage applications. This solution requires approximately 50% less logic than alternative solutions and is optimized for minimal space and low power using Xilinx® FPGAs.

“Xilinx is leveraging over a decade of expertise in error correction, DSP, and LDPC to deliver a world-class LDPC solution for the data center storage market, and is the only FPGA vendor capable of this today,” said Dr. Chris Dick, chief architect for DSP at Xilinx. The doctor also said, “We optimized the LDPC IP function to suit the unique characteristics of flash, meeting even the most demanding cloud storage requirements.”

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The Flash Memory LDPC Error Correction LogiCORE™ IP is available now for early access, with general availability starting in Q4 2015. For more information, contact your local Xilinx representative or visit www.xilinx.com/esp/datacenter/data_center_ip.htm. Xilinx will also demonstrate this product at Flash Memory Summit 2015, August 12-13, in Santa Clara, California, in booth #721.