ASIC implementation optimized for specific requirements
Reduce development cycle risk and rework risks by providing new IPs.

ON Semiconductor announced a collaboration with Hexius Semiconductor, a specialist in IP development for analog ICs, to verify several analog IP blocks in its ONC18 0.18 µm CMOS process.

ON Semiconductor stated that the eight initial designs, developed through this collaboration, include a variety of ADCs, DACs, voltage and current references, and can be customized to meet specific application requirements. IP for data converter and PLL designs is currently under development, with release planned for the second half of this year.

Additionally, ON Semiconductor's ONC18 process is said to be suitable for automotive, industrial, military, and medical development due to its high-voltage capacity based on a 0.18 micrometer (µm) CMOS architecture.


▲Capture from Hexius Semiconductor homepage.

Customers have access to a broad portfolio of IP supporting this process, allowing them to benefit from ASIC implementations optimized for their specific requirements without having to dedicate significant in-house engineering resources to the task. This results in faster design cycles and reduced risk of rework.

“The mixed-signal ASIC market continues to grow as systems increasingly need to leverage real-world data captured by sensors and user interfaces,” said Rocke Acree, director of the Custom Foundry business unit at ON Semiconductor. “OEMs want to integrate more efficient proprietary designs rather than relying on standard off-the-shelf components or silicon, which can boost performance while saving board space and significantly reducing unit cost. Working together, our companies will enable new mixed-signal designs by providing proven analog IP that facilitates this.”