Providing highly integrated timing solutions

Silicon Labs announced the launch of a new family of high-performance clock generators that provide high-density timing solutions for 10/25/100G applications.

Based on Silicon Labs' proven MultiSynth fractional clock synthesis technology, the new Si5332 clock family is a timing solution that provides best-in-class frequency flexibility and 230fs rms jitter performance. Various Si5332 options, scalable to 6, 8, or 12 clock outputs, provide integrated clock trees for demanding applications including hyperscale data center switches, servers, storage, networking, small cells, broadband, broadcast video, multifunction printers, and other industrial applications.

James Wilson, Senior Marketing Director for Timing Products at Silicon Labs, said, “Hyperscale data centers are rapidly moving from 10G to 25G, 50G, and 100G Ethernet to accelerate data transfer speeds and network efficiency. "This new investment cycle is driving equipment manufacturers to upgrade switches and access ports at a faster pace and adopt higher-performance timing solutions," they stated, explaining that "by selecting Silicon Labs' Si5332 any-frequency clock, system designers can optimize their clock tree designs without compromising timing performance."

The Si5332 family is optimized to provide reference timing for high-speed serial interconnects used in next-generation data centers. The new product supports PCI Express, the standard that has long dominated the market for interconnecting microprocessors, networking, storage, and memory.

Other industry consortia, including CCIX, Gen-Z, NVLink, and OpenCAPI, are actively developing serial interconnect replacement technologies that support data transfer speeds of up to 25 GT/s. In addition to requiring low jitter clocks, some of these solutions also require spread-spectrum reference clocks.

Since spread-spectrum clock generation is possible for each individual output, a single clock device can simultaneously support a combination of spread and non-spread clocks. Consequently, due to these features, the Si5332 family can be considered the best solution for providing reference timing for high-speed serial interconnects.

The Si5332 clock generator was designed to simplify clock tree design without compromising system performance or increasing power consumption. The new product family combines two MultiSynth floating-point clock synthesizers with five independent integer dividers, eliminating the need for a fixed-frequency clock and oscillator for clock generation.

With jitter performance of 230fs rms, the Si5332 Clock provides 2 to 5 times lower jitter than competing solutions and offers margin for 10/25/100G SerDes timing requirements. The Si5332 Clock integrates extensive on-chip power supply regulation, eliminating the need for expensive discrete LDO (low dropout) regulators required by competing solutions. The Si5332's MultiSynth-based architecture is optimized for power consumption, consuming 50 to 60 percent less power than competing solutions.