HDL Verifier R2019b,
UVM components and in Simulink
Automatic support for test bench generation


MathWorks today announced support for the Universal Verification Methodology (UVM) for FPGA and ASIC designs in HDL Verifier, included in the latest release 2019b (R2019b) of MATLAB and Simulink.

Universal Verification Methodology (UVM) is a standardized methodology for integrated circuit design verification established in 2009 by Accellera, a standards organization in the field of electronic design automation.

It mainly borrows the Open Verification Methodology (OVM) based on the hardware verification language 'e Reuse Methodology (eRM)' that can implement flexible and reusable verification test benches. The UVM class library provides automation support applicable to the SystemVerilog language.

HDL Verifier enables design verification engineers developing FPGA and ASIC designs to generate UVM components and test benches directly from Simulink for use in simulators that support UVM, such as Synopsys, Cadence, and Mentor Graphics.

According to a recent survey by Wilson Research Group, engineers and designers are using UVM for design verification in approximately 48% of FPGA design projects and approximately 71% of ASIC design projects.

Historically, algorithm developers and system designers have primarily developed new algorithms using MATLAB and Simulink, and then design verification (DV) engineers have hand-coded RTL test benches by referencing MATLAB and Simulink models.

DV engineers can now reduce the time spent manually creating test benches by automatically generating UVM components, such as sequences and scoreboards, from system-level models already developed in Simulink via HDL Verifier.

This approach helps DV engineers reduce test bench development times for ASIC and FPGA designs in areas such as wireless communications, embedded vision, and control.

“Simulink has enabled us to reduce the time it took to manually create production UVM test benches, test sequences, and scoreboards by about 50 percent,” said Khalid Chishti, ASIC development manager at Allegro Microsystems.

Meanwhile, “Allegro uses UVM for production verification of ASICs being developed for automotive applications. “We are using MATLAB and Simulink to simplify the cumbersome algorithm development work for ASIC verification devices,” he said.

HDL Verifier, which includes the ability to generate UVM components, SystemVerilog assertions, and SystemVerilog DPI components from MATLAB and Simulink, provides enhanced support for DV teams responsible for production verification of ASICs and FPGAs.

Traditionally, DV teams had to manually write code in SystemVerilog to develop rigorous test benches using an HDL simulator. HDL Verifier helps DV teams generate verification components directly from existing MATLAB and Simulink models and reuse those models to quickly set up a production verification environment.

“DV engineers spend about a fifth of their time developing test benches on ASIC and FPGA projects,” says Eric Cigan, senior HDL product marketing manager at MathWorks, citing a 2018 functional verification study conducted by Wilson Research and Mentor Graphics.

“The HDL Verifier announced this time will increase the productivity of DV engineers through the ability to generate UVM and SystemVerilog DPI components from existing MATLAB and Simulink models,” he said. “At the same time, it is expected to increase the efficiency of collaboration between system designers, hardware engineers, and DV engineers.”

HDL Verifier R2019b is ready to use.
kr.mathworks.com/products/hdl-verifier