MathWorks Supports Automation of FPGA/ASIC-Based Vision System Design with Vision HDL Toolbox R2019
Published2020.02.27 12:17Automatic generation of verified code for processing
MathWorks announced on the 27th that it supports native multi-pixel streaming for High Frame Rate (HFR) and high-resolution image processing on FPGAs through the Vision HDL Toolbox included in MATLAB and Simulink Release 2019b.
The Vision HDL Toolbox accelerates the task of video, image processing, and FPGA design engineers in exploring or simulating trade-offs between system behavior and implementation when processing 4K or 8K video, or high-resolution video at 240 frames per second or higher.
FPGA design engineers face the challenge of meeting throughput, resource usage, and power consumption targets to implement real-time processing of high-resolution and HFR images in applications such as industrial inspection, medical imaging, information, surveillance, and reconnaissance (ISR).
The Vision HDL Toolbox provides blocks that process 4 or 8 pixels in parallel, and simulates with specified parallel processingAutomatically updates the underlying hardware implementation to perform ration and code generation.
These features enable hardware engineers to collaborate with image and video processing engineers to explore and simulate vision processing hardware behavior at a high level of abstraction.
Furthermore, by adding an HDL coder to this design workflow, it is possible to directly combine with verified high-level models and generate target-independent, optimized VHDL or Verilog code.
Vision HDL Toolbox R2019b is available right now.
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