Versal HBM Reduces Memory Bottlenecks by Integrating HBM2E
Implemented Based on Proven 7nm Versal Devices
Sample Shipments Scheduled for First Half of Next Year, Tools Available in Second Half of This Year


Real-time, high-performance applications experience bottlenecks due to memory bandwidth and can operate at the boundary of power and thermal limits. In response, Xilinx announced on the 15th the launch of the latest series of its Versal portfolio, the Versal™ HBM Adaptive Compute Acceleration Platform (ACAP).

The Versal HBM ACAP integrates HBM2E DRAM offering throughput of 820GB/s and capacity of 32GB, delivering 8x memory bandwidth compared to DDR5 adoption and 63% lower power consumption. The Versal HBM series eliminates memory bottlenecks, enabling data center and network operators to deliver solutions with significantly higher performance while reducing system power consumption, latency, form factor, and total cost of ownership.

Versal HBM devices, implemented based on the Versal Premium series, integrate power-optimized networking cores for high bandwidth and secure connectivity. The Versal HBM series provides 5.6Tb/s serial bandwidth based on 112Gb/s PAM4 transceivers, scalable Ethernet bandwidth of 2.4Tb/s, encryption throughput at 1.2Tb/s line rate, 600Gb/s Interlaken connectivity, and PCIe® Gen5 bandwidth of 1.5Tb/s with embedded DMA supporting both CCIX and CXL.

As an adaptive and heterogeneous platform, the Versal HBM series integrates adaptive engines for low-latency hardware parallel processing, DSP engines for AI inference and signal processing, and scalar engines for embedded computing, platform management, secure boot, and configuration, designed to accelerate a wide range of workloads based on large datasets. Unlike fixed-function accelerators, hardware can be dynamically reconfigured within milliseconds to evolving algorithms and new protocols, eliminating the need for hardware redesign and reconstruction.

Additionally, it delivers high performance and power efficiency for big data workloads including fraud detection, recommendation engines, database acceleration, data analytics, financial modeling, and deep learning inference for natural language processing (NLP). With significantly higher runtime than the latest server-grade CPUs and support for datasets 4x larger, users can build applications with large-scale connected datasets using fewer, lower-cost servers.

It also provides network scalability and performance for 800G routers, switches, and security appliances. Existing 800G next-generation firewalls implemented with NPUs (Network Processing Units) required multiple NPU devices and DDR modules. A single Versal HBM ACAP eliminates external memory and performs packet processing, security processing, and adaptive AI-infused anomaly detection capabilities in a low-power, compact form factor.

Xilinx stated that the Versal HBM ACAP enables customers to implement applications using fewer devices and systems, allowing cloud and network providers to significantly reduce capital expenditures (CapEx) and operating expenses (OpEx).

The Versal HBM ACAP, accessible to both hardware and software developers, is supported by the Vivado® Design Suite for hardware developers, the Vitis™ integrated software platform for software developers, domain-specific frameworks and acceleration libraries, and Vitis AI for data scientists.

The Versal HBM series is implemented based on 7nm Versal devices with completed production validation. Developers can begin prototyping with Versal Premium series devices and evaluation boards and easily migrate to the Versal HBM series. The Versal HBM series is scheduled to begin sample shipments in the first half of 2022. Documentation is currently available, and tools will be accessible through an early access program in the second half of 2021.