Power supply output capacitors (typically ceramic capacitors, with values ranging from 100 nF to 100 μF) are expensive, occupy space, and sometimes difficult to obtain due to supply shortages. Therefore, designers often ask themselves, "How can I minimize the number and size of output capacitors?"

There are two main effects of output capacitors: the effect on output voltage ripple and the effect on output voltage when load transients occur.

Before that, we need to first understand the term output capacitor. This refers to the capacitor used at the output of the power supply.

However, electrical loads such as FPGAs also require a specific number of capacitors at their inputs.

Figure 1 shows the power supply design and the FPGA as a load. When the physical distance between the voltage generating side and the voltage consuming side on the circuit board is close, it can be difficult to clearly distinguish between the power supply output capacitor and the load-side input capacitor.

In such cases, physical separation can be used to achieve separation, but this can result in significant parasitic inductance (Llayout).





The capacitor configuration at the power supply output determines the voltage ripple of a step-down (buck) switching regulator. The principle that the output ripple voltage is equal to the inductor ripple current multiplied by the output capacitor impedance applies here as well.







This impedance ZCout includes not only the size and number of capacitors, but also the equivalent series resistance (ESR) and equivalent series inductance (ESL). If you have a single capacitor at the power supply output, this formula can be applied quite easily.

However, in complex cases where multiple capacitors are used in parallel as in Figure 1 and series inductance (Llayout) occurs due to the layout, the calculation is by no means simple.





In such cases, simulation tools such as LTspice® can be used. Figure 2 shows a quickly generated schematic for the situation in Figure 1. Various values, including ESR and ESL, can be specified for individual capacitors. The effects of board layout (e.g., Llayout) can also be considered. Voltage ripple at the switching regulator output and load input can then be simulated.

The output capacitor also affects the output voltage offset after a load transient. This effect can also be simulated using LTspice. It's important to note that the control speed of the power supply control loop and the impedance of the output capacitor are interrelated. A faster power supply control loop reduces the number of output capacitors required to maintain the output within a specified control range after a load transient.

The LTC3311-1 offers a feature called Adaptive Voltage Positioning (AVP). AVP widens the loop bandwidth based on the input error voltage budget, further reducing the number of output capacitors.

The AVP function slightly increases the output voltage under low load conditions and slightly decreases it under high load conditions, ensuring that dynamic output voltage fluctuations during load transients remain within the acceptable output voltage range.

Using LTpowerCAD® from Analog Devices, you can determine how to optimize the control loop and reduce the output capacitor. Figure 3 shows a screen shot of the control speed calculation. This shows a voltage overshoot following a load transient. Optimization can be achieved by adjusting the output capacitor configuration and the switching regulator control loop speed.

This optimization allows us to reduce the number of output capacitors in the power supply, thereby saving cost and board space.

※ The above article is a contribution by Frederik Dostal, FAE, Analog Devices, Inc.