Panesia (CEO Myeongsu Jeong), a core link solution company in the AI infrastructure and HPC (high-performance computing) field, has established itself as a leading next-generation interconnect technology company in the global AI data center and HPC market by presenting a new paradigm for AI/HPC workload acceleration with its self-developed CXL 3.2/PCIe 6.4 fabric switch and MPI-over-CXL solution.

Panesia announced on the 24th that it unveiled its next-generation CXL 3.2/PCIe 6.4-based fabric switch solution at the world's largest supercomputing event SC25 (St. Louis, Missouri, USA) and the global data center event OCP Global Summit 2025 (San Jose, California, USA).

At this exhibition, Panesia actively participated in international standardization activities by presenting on the official panel of the CXL Consortium together with Intel, AMD, and Micron.

The PCIe 6.4/CXL 3.2 fabric switch node introduced by Panesia features innovative technology that integrates thousands of devices into a single fabric for large-scale AI and HPC applications.

Panesia said, “It effectively accelerates desired applications by making devices distributed across multiple server racks work as if they were one giant accelerator.”o; explained.

This solution offers two key capabilities: connecting thousands of devices and optimizing fabric-wide performance. Specifically, it enables ultra-low latency connectivity using only CXL-based interconnects, bypassing the network, resulting in a dramatic performance boost over traditional Ethernet.

Panesia switches support port-based routing (PBR), allowing you to freely configure various data center topologies such as torus and dragonfly.

This is what differentiates it from existing CXL switches that only support tree structures. Additionally, when the connection method is changed, the internal routing structure is automatically reconfigured, minimizing manual work by engineers and significantly increasing operational efficiency.

The Panesia switch supports PCIe 6th generation 64GT/s transmission speed and is equipped with a self-developed ultra-low latency CXL controller to achieve double-digit nanosecond latency.

Additionally, the cache consistency guarantee function minimizes unnecessary data movement and reduces performance degradation due to communication.

Based on this, we have proven that various workloads such as augmented search generation (RAG) and MPI-based scientific simulation can be effectively accelerated.

At the SC25 event, Panesia presented its MPI-over-CXL solution in a panel session titled “How To Leverage CXL Memory Pooling and Sharing for AI and HPC Workloads” with Intel, AMD, and Micron.

The existing MPI (Message Passing Interface) method had the problem of performance degradation due to data copying between CPUs, but Panesia's solution minimized data copying by applying a memory sharing-based pointer exchange method.

A Panesia official emphasized, “We can innovatively accelerate HPC applications by utilizing the memory sharing function of the CXL 3.2 controller, which we developed using domestic technology.”