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AMD Targets Industrial Fields with Ultra-Low-Power Edge Performance

Google 우선 소스Published2025.12.12 08:48

EPYC Embedded 2005 Series Optimized for Networking, Storage, and Industrial Systems

In the era of AI and cloud, the demands on industrial infrastructure are becoming increasingly demanding. High-density compute performance, power efficiency, and long-term stability are simultaneously required across diverse fields, including network switches and routers, data processing unit (DPU) control, cold cloud storage, aerospace, and robotics. AMD is targeting the next-generation embedded infrastructure market with ultra-low-power edge.

AMD announced on the 10th that it has launched the EPYC Embedded 2005 series processor.

The new product is a 40mm x 40mm BGA package, boasting a size that is 2.4 times smaller than the comparable Intel Xeon 6500P-B.

This allows designers to achieve higher I/O density and shorter electrical paths, simultaneously improving signal integrity and heat management.

It is equipped with up to 16 x86 cores and 64MB L3 cache, and can precisely adjust the TDP range from 45W to 75W to respond to various power and thermal environments.

In particular, compared to the Xeon 6503P-B, it achieves a 35% increase in base CPU frequency and a 28% increase in boost frequency with half the power, achieving both performance density and cost efficiency.

EPYC Embedded 2005 comes with up to 10 years of field operation warranty and 15 years of software maintenance. It provides long-term investment stability.

Additionally, RAS (Reliability, Availability, and Serviceability) features detect and correct errors in advance to minimize downtime.

It also includes BMC support, PCIe hotplug, and multi-SPI ROM capabilities for networking and storage environments.

On the security front, AMD Infinity Guard is key. AMD Secure Processor, Platform Secure Boot, and Memory Guard enhance data integrity and system reliability, providing peace of mind even in mission-critical environments.

The new product provides 28 PCIe Gen5 lanes to support high-speed NIC, FPGA, and network ASIC integration.

It also provides higher bandwidth with DDR5 memory and provides a smooth transition path for DDR4 as it nears its end of life.

Developers can leverage a rich open source ecosystem, including Yocto, kernel drivers, and EDK II, to simplify integration and accelerate time to market.
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