· Based on Intel 14nm Tri-Gate and featuring the innovative HyperFlex architecture, Stratix 10 FPGAs and SoCs deliver twice the performance and exceptional power efficiency.

· Ushering in a new era of heterogeneous 3D SiP (system-in-package) integration, it enables scalability and flexibility for next-generation transceiver-based solutions and reduces time to market.

· Delivers the industry's most comprehensive set of high-performance FPGA security features by introducing the innovative Secure Device Manager.

HONG KONG, June 9, 2015 – Altera (NASDAQ: ALTR) today announced architectural and technical details for its Stratix® 10 FPGAs and SoCs. The Stratix 10 family is Altera's next-generation family of high-end programmable logic devices that deliver significant improvements in performance, integration, density, and security.

Stratix 10 FPGAs and SoCs are based on Intel®'s 14nm Tri-Gate process and utilize Altera's innovative HyperFlex™ FPGA fabric architecture to deliver 2x higher core performance than previous-generation FPGAs. By combining the industry's highest-performance and highest-density FPGAs with advanced embedded processing, GPU-class floating-point performance, and heterogeneous 3D SiP integration, it enables customers to meet the demanding needs of next-generation communications, data centers, IoT infrastructure, defense, and high-performance computing systems in ways never before possible.

“The performance we deliver with our Stratix 10 FPGAs and SoCs is unprecedented in the industry,” said Danny Biran, senior vice president of marketing at Altera. “Stratix 10 FPGAs and SoCs enable our customers to design systems and innovate in ways never before possible with FPGAs.”

HyperFlex Architecture Brings Registers Everywhere

Stratix 10 FPGAs and SoCs are the first Altera devices to incorporate Altera's new HyperFlex architecture, which is expected to be the most significant fabric architecture innovation in the FPGA industry in a decade. Combining the process node advantage of Intel's 14nm Tri-Gate process with the HyperFlex architecture delivers a 2x core logic frequency increase over competing next-generation high-end FPGAs.

By introducing registers into every core interconnect routing area, the HyperFlex architecture enables Stratix 10 FPGAs and SoCs to leverage proven performance-enhancing design techniques, including register retiming, pipelining, and other design optimizations. These design techniques were not feasible with existing FPGA architectures. The HyperFlex architecture eliminates critical path and routing delays, enabling designers to quickly achieve timing closure on their designs. It also delivers twice the core logic performance, significantly improving device utilization and power by eliminating the need for the extremely wide data paths and other skew-inducing structures required by competing architectures. By reducing the required logic area, the HyperFlex architecture enables high-performance designs to operate at up to 70 percent lower power. More information about this architecture can be found at www.altera.com/hyperflex.

The Era of Heterogeneous 3D SiP Integration Begins

All members of the Stratix 10 FPGA and SoC families leverage heterogeneous 3D SiP integration technology to efficiently and cost-effectively integrate high-density monolithic FPGA core fabric with other advanced components, thereby increasing the scalability and flexibility of Stratix 10 FPGAs and SoCs. The monolithic core fabric maximizes device utilization and performance by avoiding the interconnect challenges associated with competing heterogeneous devices that require multiple FPGA dies to achieve high density. Altera's heterogeneous SiP integration is made possible by leveraging Intel's patented Embedded Multi-die Interconnect Bridge (EMIB) technology, which delivers higher performance, reduced complexity, lower cost, and improved signal integrity compared to interposer-based approaches.

The first products in the Stratix 10 family use EMIB technology to integrate high-speed serial transceivers and protocol tiles with monolithic core logic. By integrating high-speed protocols and transceivers into heterogeneous 3D SiPs, Altera can rapidly deliver different Stratix 10 device product variants to meet evolving market needs. For example, heterogeneous 3D SiP integration enables Stratix 10 devices to quickly support higher transceiver speeds (56 Gbps), emerging modulation formats (PAM-4), new communication standards (PCIe Gen4, Multi-Port Ethernet), and other features such as analog or high-bandwidth memory.

The Stratix 10 family of devices, available in a variety of densities, integrates a 64-bit ARM® quad-core Cortex®-A53 Hard Processor System (HPS) along with a rich set of peripherals including a system memory management unit, an external memory controller, and high-speed communication interfaces. With the Stratix 10 SoC, Altera further strengthens its industry-leading position as the only supplier of high-end SoC FPGAs. This versatile computing platform is ideal for a wide range of high-performance applications by delivering exceptional adaptability, performance, power efficiency, system integration, and design productivity. Designers using Stratix 10 SoCs in their high-performance systems will be able to implement hardware virtualization, as well as add management and monitoring capabilities such as accelerated preprocessing, remote update and debug, configuration, and system performance monitoring.

Achieve maximum design protection by integrating comprehensive security features.

Stratix 10 FPGAs and SoCs integrate the industry's most comprehensive security features into high-performance FPGAs. A key component of this is the innovative Secure Design Manager (SDM). Secure Design Manager provides security features such as sector-based authentication and encryption, multi-factor authentication, and physically unclonable function (PUF) technology. Altera, in collaboration with partners including Athena Group and IntrinsicID, delivers world-class cryptographic acceleration and PUF IP to Stratix 10 FPGAs and SoCs. This level of security makes Stratix 10 FPGAs and SoCs ideal for applications such as defense, cloud security, and IoT infrastructure, where multi-layered security and isolated IP protection are crucial.

Enpirion PowerSoCs available for Stratix 10 FPGAs and SoCs

Support for Altera's Enpirion PowerSoC power solutions for Stratix 10 FPGAs and SoCs. Enpirion PowerSoCs not only meet stringent performance and power requirements, but also achieve high efficiency in an extremely small footprint.

Achieving rapid timing closure with millions of LE designs

The new Spectra-Q engine, introduced in Altera's Quartus® II software, maximizes the performance, power, and area savings from the HyperFlex architecture while also improving design productivity and accelerating time to market for designers using Stratix 10 FPGAs and SoCs. Quartus II software continues Altera's lead in design software by adding new features such as up to 8x compile time reduction, multi-mode fast-tracking design entry, drop-in IP integration, OpenCL support, and a high-level design flow. More information about the Spectra-Q engine can be found at www.altera.com/spectraq.

Summary of technical features of Stratix 10 FPGAs and SoCs:

· Up to 5.5 million logic elements in a monolithic die

· Integration of FPGA fabric and high-speed transceivers through heterogeneous 3D SiP integration.

· Integrates up to 144 transceivers, providing four times the serial bandwidth compared to previous generation products.

· Integrated 64-bit quad-core ARM Cortex-A53 hard processor subsystem operating at up to 1.5GHz

· Single-precision calculations with up to 10 TFLOPS throughput are possible by integrating a hard floating-point DSP.

· Secure Device Manager: Provides comprehensive, high-performance FPGA security features.

· Advanced single-event upset (SEU) detection and scrubbing

· Footprint compatibility with Arria® 10 FPGAs and SoCs for easy migration

Maximize power efficiency and save board space by utilizing Altera Enpirion power solutions.

· Application of Intel's 14nm Tri-Gate process technology

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Designers can begin developing their Stratix 10 designs today using the Fast Forward Compile performance evaluation tool. Engineering samples of Stratix 10 FPGAs and SoCs will be available in fall 2015. Embedded software developers can accelerate Stratix 10 SoC embedded software development by leveraging the SoC virtual platform provided by Mentor Graphics. For more information about Stratix 10 FPGA and SoC products, contact your local Altera sales office or visit www.altera.com/stratix10.