Standardized Jitter Calculator for PCIe 1.0, 2.0, 3.0, and 4.0 Specifications

Silicon Labs has announced a free software tool that allows engineers to quickly and easily measure PCI Express® (PCIe®) clock jitter from oscilloscope data files with just a few clicks. Through this tool, engineers can easily verify compliance with PCIe specifications and reduce system development time.

Silicon Labs’ Clock Jitter Tool is the first standardized jitter calculator for PCIe 1.0, 2.0, 3.0, and 4.0 specifications, and is available for free to all engineers developing applications based on the PCIe architecture. Designed to support PCIe common clock and discrete clock architectures, this tool is available to anyone and is not limited to cases where Silicon Labs clock products are used.

Silicon Labs’ jitter measurement tool for PCIe technology is available to developers immediately and can be downloaded for free from www.silabs.com/pcie-learningcenter .

The PCIe standard, which was first used as a serial interconnect for desktop PCs more than 10 years ago, has now evolved into a third-generation technology and is being widely adopted in blade servers, storage, embedded computing, IP gateways, industrial systems, and consumer electronics.

PCIe technology is adopted in FPGA and SoC devices to provide a versatile, high-performance method for data transmission within the system. Although the PCIe specification specifies a 100 MHz reference clock with ±300 ppm frequency stability, some FPGA and SoC designs can operate up to 250 MHz internally, making clock jitter evaluation an important design consideration.

Some designs can operate up to 250MHz

There are often misunderstandings regarding filter masks and jitter calculations for PCIe technology during the development process. Since most oscilloscopes do not include the essential filter masks required to accurately measure PCIe clock jitter, confusion may arise regarding why the measured results do not match the datasheet specifications.

Developers sometimes report PCIe jitter measurements higher than the clock datasheet specifications, which turns out to be the result of incorrect measurements rather than design flaws. As a leading provider of PCIe clock products, Silicon Labs has designed a PCIe jitter tool to address this issue and provides hardware developers with a downloadable utility that allows them to quickly determine whether measured clocks comply with PCIe jitter requirements.

Silicon Labs’ Clock Jitter Tool for PCIe Technology provides an intuitive graphical user interface that guides developers through the few simple steps required to calculate clock jitter from oscilloscope data files. The tool includes all filter masks defined by PCI-SIG® for PCIe 1.0, 2.0, 3.0, and 4.0 common clock and discrete reference clock architectures, and supports both independent SRIS (spread spectrum) and SRNS (non-spread spectrum) methods. The jitter results are presented in a concise and easy-to-read summary that eliminates guesswork while ensuring the system design complies with PCIe specifications with sufficient jitter margins.

In related news, Silicon Labs announced that its clock generators and buffers comply with PCIe 4.0 specification requirements. All relevant product datasheets have been updated to reflect the contents of PCI Express Base Spec 4.0, rev 0.5.

James Wilson, Marketing Director for Timing Products at Silicon Labs, stated, “One of our visions is to simplify timing, and Silicon Labs has developed a clock jitter tool to help obtain PCIe jitter measurements as quickly, easily, and accurately as possible.” He added, “We are providing a free clock jitter calculator so that all developers working with the PCIe data bus standard can benefit, regardless of the supplier of the clock IC they use.”