Core-A, Mcore, and other domestic CPU core development projects, one year in the making.
A unified voice for increasing stability and reliability and expanding market awareness

"We have confirmed the potential success of domestically produced CPU cores."

As the number of commercialized products increases, the government-led domestic CPU core development project is showing visible results.

The domestic CPU core roadshow held by the Semiconductor Research Association on the 3rd featured a look back at the government project's first year. Song Yong-ho, head of the Intelligent Semiconductor Promotion Team, stated, "This project will see 1 billion won invested in six to seven fabless companies over a three-year period, from last year to next year. Despite the challenges, we have achieved commercialization of some products."

Ki-Hyeon Ahn, executive director of the Semiconductor Industry Association, also said, “It was a business with many concerns when it first started, but commercialization went well despite the risks of SoC. “The domestic fabless companies are not in a good situation, so I hope that this successful case will have an impact on other businesses,” he said.


▲A robot demonstrated using AD Chips' empress processor.

On this day, the domestic CPU core roadshow introduced Core-A of Dynarit Systems, emCore of ADCHIPS, Aldebaran of Korea Electronics and Telecommunications Research Institute, and MENSA core of Korea Electronics Technology Institute (KETI). As examples of SoC development utilizing these cores, Believe Micron's digital walkie-talkie location-based wireless communication SoC (Core-A applied), MCS Logic's USB DAC built-in wireless speaker SoC (emCore applied), and Unmanned Solution's small mobile robot platform control SoC (Aldebaran applied) participated and demonstrated products. Accordingly, E4ds News would like to introduce these domestic CPU cores and development cases in two parts.

Optimized for small-quantity, multi-variety products, Dynarit System's Core-A

Core-A is a 32-bit RISC processor developed at KAIST with support from the Korean Intellectual Property Office. The compiler and debugger were developed by Chonbuk National University and Pusan National University. Various peripheral control devices and platforms were developed by Dynalith Systems (www.dynalith.com).

Core-A is a soft core, a hardware design block that provides RTL code and can be synthesized using a logic synthesizer. In other words, it offers the advantage of providing RTL (Register Transfer Level) code and being synthesized using an industry-standard synthesizer. Through a relatively simple process and a technology agreement, it can be provided without introduction or usage fees. Dynarit Systems stated, "The advantage is that it can be tailored to the user's usage environment," and added, "Its performance is similar to that of the ARM9, a commercial processor of a similar level."


▲ Core-A processor structure (top) and software development environment

The Core-A processor provides an RTL with a bus interface that can be directly connected to the industry-standard buses AMBA AHB and AMBA AXI. In particular, the TCM version is suitable for relatively small-scale SW operations, and the cache version is suitable for relatively large-scale SW operations. The capacity of the TCM can be adjusted as needed, and the size and multi-way degree of the cache can be adjusted as needed.

Provides RTL with standard bus interface

The Core-A processor comes with a C compiler based on GNU GCC and supports the ICE-Debugger (OpenJTAG) that integrates with GNU GDB for source code-level debugging. An LLVM (Low Level Virtual Machine)-based C compiler is currently under development, with a target release date of 2017. To create system semiconductors using the Core-A processor, an environment for simultaneous hardware and software design and functional verification is required, and the CoreIDEA environment is provided for this purpose. The company said that various semiconductor design assets, such as system buses, legacy IP, audio, video, Ethernet, memory controllers, and flash, are provided.

The Core-A processor-supported application platform provides a reference design in RTL format that can be readily applied to a variety of applications, including audio, video, networking, RTOS, and file systems. In particular, uC/OS-II and FreeRTOS are pre-installed as real-time operating systems. Development boards for designing and verifying system semiconductors utilizing Core-A are available in various sizes, with application platforms pre-installed on them.


▲ Believe Micron developed a SoC for wireless communication and signal processing using Core-A.

Since its 2008 release, the Core-A processor has been steadily evolving through application design, peripheral IP development, and system support features. Currently, the version with enhanced AMBA AHB/AXI support is primarily utilized, and a cache-enabled version has been newly added for use in system semiconductor design. In the future, a version with enhanced low-power functions, security functions, and stability functions will be developed and added, and there are plans to upgrade to a version with added and enhanced lightweight and multi-processor support functions.

Dynarit Systems stated, “The Core-A processor is suitable for applications where the ARM7, ARM9, Cortex-M, and Cortex-R series are used, as well as applications where control functions are more important than data processing. Core-A can be utilized as the main processor or auxiliary processor of system semiconductors, and is also well suited for high-mix, low-volume products when applied to FPGA internal designs.”

“When Core-A is used with SPI-flash, it simplifies the booting process by directly executing code in the flash according to the XiP (eXeute In Place) function, and in some cases, code memory is not necessary,” said Vice President Ki-an Do of Dynarit Systems. “We have established a technology roadmap so that the Core-A processor can continue to be scheduled for various purposes in the future.”

Believe Micron can differentiate its source code and pricing, but needs to improve its market awareness.

Believe Micron Co., Ltd. developed a wireless communication and signal processing SoC for location-based services of digital radios by applying Core-A. The goal is to build a communication network for radios by developing distance extension and communication maintenance technology that incorporates a mobile Ad-Hoc network, and to develop a network radio SoC that supports positioning information, voice signal processing, and data sharing between terminals by utilizing domestically produced CPU cores in the built network environment.

Jaehong Eom, CEO of Believe Micron, said, "We differentiated our products by securing price competitiveness through the use of domestically produced cores and offering a differentiated service solution with added positioning capabilities." This SoC is particularly notable for its cache-supported XIP, which eliminates flash memory, reducing memory footprint and ensuring reliability.

CEO Eom, who developed SoC by applying Core-A, said, “If we analyze the competitiveness of the core, the strengths include differentiation in source code and price, performance improvement through compiler optimization, and software emulators,” and pointed out, “On the other hand, there is a need to reduce SRAM/Flash memory requirements, improve market awareness, and present differentiating features in performance and fields separately.”

ADCHIPS emCore: Competing Against Powerful Overseas CPU Cores

While the famous microprocessor architectures overseas include CISC (developed by Intel, Motorola, AMD, etc.) and RISC (ARM, MIPS, etc.), Korea has 'EISC'.

ADCHIPS' EISC (Extendable Instruction Set Computer) was evaluated as having both the simplicity of RISC and the expandability of CISC. CISC (Complex Instruction Set Computer Architecture) has a complex variable instruction set architecture, but a small code size, while RISC (Reduced Instruction Set Computer Architecture) has a fixed instruction set architecture, resulting in a large code size but simple hardware. Compared to these architectures, EISC, which appeared relatively later in 2000, has the advantages of simple hardware and small code size due to its extended instruction set architecture.

While EISC was created to differentiate itself from existing foreign architectures, it has also been causing confusion with the brand, leading to the recent decision to use the generic name "emCore." EmCore is a domestically produced CPU core based on the EISC architecture.


▲ A drone demonstrated using ADCHIPS' empress processor.

EISC is an ISA (Instruction Set Architecture) for embedded processors developed by ADCHIPS. It introduces a new concept called extended instructions and has an excellent code size with a dual fixed instruction structure of 16-bit and 32-bit instruction lengths. ADCHIPS stated, “The mCore also has a fixed instruction structure, so the hardware is simple, and the number of GPRs is large, which reduces flash memory access and enables low power consumption. Its 16-bit instruction structure reduces flash memory access by fetching two instructions at a time.” In particular, it is easy for customers to add or modify new instructions they want through ADCHIPS’ original CPU technology.

While differentiating itself from competing processors and technologies, Emcore also clearly targets its target. The strategy is to avoid meaningless competition with existing players like ARM, Intel, Samsung, and Qualcomm, and to avoid entering the saturated mobile processor market. Instead, the company plans to expand its market by first entering the mid-market, such as embedded and microcontrollers.

Accordingly, ADCHIPS commercialized five domestically produced 32-bit mCore series products, including the low-end SE1608, SE3208, and Tiny product lines, as well as the Lucida and Empress series, and supplied them to domestic large and small businesses such as LG Electronics, Samsung Electro-Mechanics, Samsung Techwin, Inix, and Chips & Media. The company stated that the cumulative shipment of mCore-based chips to date has exceeded approximately 50 million units.

EmCORE provides customers with AMBA bus-based SoC platforms. The emCORE SoC platform, which includes AMBA bus-based CPU cores and peripheral blocks, shortens customer development times and helps them get to market faster.

Supported CPU core technologies include an integrated development environment (IDE) and compiler, along with a JTAG debugger and downloader. Hardware and software manuals are available, and after specification negotiation, the core platform is redesigned and delivered to the desired specifications. Furthermore, pre-simulation and post-simulation guides are provided for SoC design verification, along with EDF files and various APIs for FPGA download and verification. We support both SoC and FPGA design with CPU core technologies.

With the development of its second-generation CPU core ISA, mCore Technology plans to enter the ultra-light CPU market targeting IoT wearables and the high-performance mobile CPU core market. The second-generation mCore JUNO processor series features expanded instructions and delivers more powerful performance than previous generations while maintaining similar power consumption and code size. In addition, the second-generation processor, which has a structure that increases power efficiency through improved power management, was developed with an ISA structure suitable for Super-Scalar, Virtual OS, and 64-bit machines over 1 GHz.

Encryption-related commands were added, and a monitor mode supporting 32 coprocessors was added for efficient support of GP-GPU array processors. Regarding the commercialization roadmap strategy, ADChips stated, “We have completed core hardening of three types of cores: SE1608, Tiny, and Lucida cores on China’s CSMC 0.18um process,” and “We are promoting IP registration of domestically produced CPU cores to Samsung Foundry.” In addition, we plan to build an SoC platform that can be used according to industrial characteristics in the future, and we plan to develop a mid- to low-priced mCore series targeting the IoT, wearable, smart home appliance, and automotive application markets.

Lee Hee, Vice President of AD Chips, said, "The most fundamental element of a microprocessor is the ISA, or 'instruction set.' Many ISAs have been developed and then disappeared from the market. “The background behind the creation of the Mcore EISC was to develop a competitive ISA compared to existing microprocessors without infringing on patents,” he said.

“Currently, Emcore is being applied in various fields such as kitchen appliances like electric rice cookers, home appliances, medical devices, golf GPS, door locks, Hi-pass terminals, voice recognition, wireless modems for IoT, smart power metering, and touch sensor controllers,” said Vice President Lee, who is developing the second-generation JUNO S series with Emcore’s full command set developed. “It also supports robots and drones, but actual sales are generated from smart appliances and IoT.”

MCS Logic Develops Single-Chip Audio System Semiconductor for Wireless Speakers

MCS Logic is developing a SoC for wireless speakers with a built-in USB DAC using MCore. The specific development task is to develop a single-chip audio system semiconductor for wireless speakers, featuring a built-in USB DAC capable of processing 7.1-channel, 32-bit, 384kHz high-quality audio.

Kim Chan-sik, head of research at MCS Logic, highlighted the pros and cons of using Empress for hardware and software development. First, regarding hardware development, he noted, "Empress's architecture allows for relatively flexible changes, and requests for CPU and bus clock changes are easily accommodated." He added, "Furthermore, it eliminates the need for additional design and supports a variety of FPGA devices." However, Director Kim pointed out that “Once Empress is stabilized, the input/output ports and delivery form need to be confirmed, and if it is not easy to fix the input/output ports, there needs to be documentation on the modification points,” and “there is a disadvantage in that program debugging is very difficult because register monitoring is not possible.”

In terms of software, he said, “The GNU-based toolchain can be used not only in Linux but also in MS Windows environments through Cygwin, and the program portability is good because it uses a GNU-based compiler,” but “on the other hand, the limitations of the OS environment and the poor compiler optimization performance are problems.”

☞Next week, articles related to the Aldebaran processor and Mensa processor will be updated.