Intel Announces Per-Core Performance Improvements and Enhancements for Intel Xeon Scalable Processor Family

Intel participated in the 2017 International Supercomputing Conference (ISC) and announced that HPC systems must evolve to enable new levels of performance, scalability, memory, bandwidth, and I/O capabilities to handle various workloads.

In addition, we discussed how users can obtain value of a magnitude previously unattainable through new approaches to HPC system design and flexible implementation models.

Intel unveiled recent achievements at ISC 17 that can further advance HPC systems and bring new experiences to supercomputing users. Intel announced per-core performance improvements and other enhancements for the upcoming Intel Xeon Scalable processor family, explaining how these improvements can support a wide range of workloads.



The Intel Xeon Scalable family of processors incorporates Intel Advanced Vector Extensions 512 (Intel AVX-512) to provide the performance boost needed in heavy and demanding usage scenarios through a 2x peak improvement in FLOPs (floating-point operations) per clock cycle. Combined with improvements in cores, cache, and memory, Intel Advanced Vector Extensions 512 delivers up to 2.27x performance improvement compared to the currently used Intel Xeon E5 v4 (codename Broadwell) processors, and up to 8.2x more double-precision gigaflops per second compared to the Intel Xeon E5 family of processors that are four years old.

In addition, the Intel Xeon Scalable processor family combines the Intel Omni-Path Architecture (Intel OPA), a high-bandwidth and low-latency fabric for performance optimization, to provide the performance required for processing today's HPC workloads and the capability to scale to tens of thousands of nodes, while enabling TCO reduction.

In addition, Intel announced the Software Defined Visualization Appliance (SDVis Appliance), an open standard-based turnkey solution. This solution enables HPC users to benefit from an already developed software ecosystem without the need to collaborate with vendors for customization when building or assembling hardware systems themselves.

During the keynote speech at the event, Intel HPC experts Rajeeb (Raj) Hazra and Patricia (Trish) A. Damkroger shared Intel's plans to develop HPC systems capable of high-performance data analysis by combining traditional HPC with artificial intelligence. The goal is to integrate Intel's upcoming products targeting AI applications to enable HPC to process workloads faster and at a lower cost. Intel stated that through this, they aim to make HPC the foundation driving new digital services and experiences while ensuring the stability and efficiency of those services.