ARM Uses Mentor 'PowerPro' for Entire IP Class Design Process
Tell the RTL designer where power can be saved.

The challenge of semiconductor designers attempting low-power design has brought them one step closer to 'minimizing power consumption'.

This refers to the result of the collaboration between ARM, a provider of representative scalable high-performance IP, and Mentor Graphics, the developer of the low-power PowerPro platform. ARM, which supplies low-power architectures for low-power mobile applications, automotive solutions, and the Internet of Things, maintains a low-power approach throughout its design, which is also applied to power-efficient RTL IP design.

The problem is that the workload of RTL designers handling power during the design process is increasing. Consequently, it has become necessary to inform RTL designers where power can be saved in the design, and Mentor Graphics' 'PowerPro' has become a highly efficient guide for this. The 'PowerPro' platform enables the easy implementation of the lowest-power RTL during design by providing an interactive approach to power exploration and reduction.

In other words, to efficiently realize low-power goals, the development flow must be automated, and ARM used the 'PowerPro' RTL power platform to analyze RTL and gate-level power, or to explore and reduce RTL power. In addition, ARM utilizes PowerPro in the design process of entire ARM IP classes, such as connecting CPUs, GPUs, interconnect subsystems, and display cores to meet power targets.

According to the low-power IP design flow methodology used by ARM designers to address power issues with PowerPro technology, obtaining gate-level power figures, for example, may take several days, but RTL power analysis of a CPU/GPU takes only one hour. This is because RTL power analysis is significantly faster than gate-level power analysis, which requires the completion of physical implementation.

In addition, low-power goals can be optimized by utilizing power optimization suggestions provided by the tool, such as Combinational/Sequential Redundancy, which can reduce power by thoroughly analyzing power reports.

ARM assessed that as a result of using the PowerPro platform, it was able to secure a power-centric RTL design flow. The PowerPro platform was the foundation behind the improvement in RTL design efficiency.