CPU, GPU, FPGA, ASIC, etc. are used for AI acceleration
Moore's Law Breaks Down, Slowing Performance Improvements
Neuromorphic semiconductors that mimic the human brain are in the spotlight


AI has cognitive abilities that are equal to or better than those of humans. Today, most companies are exploring ways to use AI in their business.

As companies undergo digital transformation, they are strengthening the AI functions of their existing IT resources. Using AI accelerators is one way to do so.

AI accelerators are hardware that support fast processing of AI algorithms and are designed to efficiently perform specific AI-related tasks that are inefficient with x86-based CPUs.

AI accelerators use processors such as CPUs, GPUs, FPGAs, and ASICs. CPUs are the best in terms of general usability, and ASICs are the best in terms of suitability. The problem is that as Moore's law reaches its limit, we cannot expect dramatic performance improvements or increased power efficiency. The concept that emerged in response is neuromorphic semiconductors.

IBM has been involved in the U.S. Department of Defense's SyNAPSE project since 2008 and created a neuromorphic chip, TrueNorth, in 2014. TrueNorth can classify images at 1,200 to 2,600 frames per second with a power of 25 to 275 mW, which is 1/10,000th of that of existing processors. It is a good example of the low-power performance of neuromorphic semiconductors.

According to the 'Artificial Intelligence Neuromorphic Semiconductor Technology Trends' published by the Electronics and Telecommunications Research Institute (ETRI) on June 1, the human brain operates in a different way from computers. Computing systems that follow the von Neumann architecture are optimized to transmit and modify precise numerical representations of data. On the other hand, the human brain operates on temporal events called action potentials or spikes.

Neurons receive spikes across synapses and convert them into small changes in the cell membrane potential, and neurons integrate these potential changes over time. When many spikes arrive in a short period of time, the neuron finally outputs a spike.

Spikes can be considered messages in a computational sense, but they are very simple and different from the traditional concept of messages in that they do not contain any information other than the time and source at that point in time. Therefore, computing in the brain can be said to be an event-based operation that communicates through very simple messages called spikes, based on computing nodes (neurons) with a very simple structure.

It is estimated that there are about 10 ¹¹ neurons in the human brain, with about 5,000 to 10,000 synapses per neuron.

The probability that a single neuron can receive a signal from another neuron is about 10 ^-6 %, indicating a sparse signaling connectivity, which is even smaller when considering that a single dendrite can form multiple synapses.

Instead, the fan-out connectivity of neurons is very large, with an estimated 10 ¹⁵ connections across the brain. That is, the probability of receiving a signal is very low, but there are many paths for the signal to come in.

Neuromorphic computing platforms based on spiking neural networks (SNNs) aim to efficiently mimic biological spiking neural network mechanisms by distributing information through synaptic computation and information storage via an event-based asynchronous spike operation mechanism across a large number of relatively simple computational units, such as neurons.

The event-based asynchronous operation characteristics of SNNs are known to greatly increase parallelism and significantly reduce hardware energy consumption. Moreover, combining SNN neuromorphic hardware with nano-scale memory devices is expected to achieve even higher energy consumption efficiency goals.

◇ Neuromorphic semiconductors, combining with memory semiconductor technology is important

Most neuromorphic semiconductors developed to date have been implemented using only existing silicon-based CMOS transistor technology. If this is called the first-generation neuromorphic method from the perspective of the implementation device, then the neuromorphic semiconductors implemented as next-generation neuromorphic devices can be called the second-generation method.

In the first generation of neuromorphic semiconductors, synapses were implemented by storing and then reading synaptic weights using existing CMOS memory devices.

In the industry, research is being conducted to implement second-generation neuromorphic semiconductors by utilizing memristor devices that have both the functions of memory and variable registers.

Memristor is a combination of the words memory and resistor. It must be small in size and have gradual switching resistance characteristics for detailed weighting.

Second-generation neuromorphic semiconductors include flash memory, resistive RAM (RRAM), phase-change memory (PRAM), and magnetic RAM (MRAM) depending on the device materials and implementation method, and the memristor method is currently being studied the most.

Second-generation neuromorphic semiconductors have been studied at the unit function block level, but recent developments have focused on testing the feasibility of implementation at the system level.

As the number of cases utilizing AI increases across all industries, interest in CPU, GPU, FPGA, and ASIC-based AI accelerators is naturally increasing. However, the processors used in these accelerators are power-hungry, unlike the human brain, and ironically, their data processing is also inefficient.

If neuromorphic technology-based semiconductors are commercialized, AI will be able to overcome the limitations of existing computing systems and further demonstrate its potential in various industries.