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Overcoming Reticle Limitations with Foveros, EMIB, and EMIB-T, Expanding AI Chiplet Connectivity
As the demand for AI computing surges, the semiconductor design paradigm centered on a single large chip is changing. Intel has entered the competition to realize next-generation AI semiconductors by launching full-scale development of advanced packaging technology based at its production facility in New Mexico.
Intel disclosed on the 30th the progress and status of its advanced chip packaging process currently underway at its Fab 9 production facility in Rio Rancho, New Mexico.
It announced that it is strengthening chiplet connectivity scalability and AI workload processing capabilities centered on three technologies: Foveros stacking, EMIB (Embedded Multi-Die Interconnect Bridge) silicon bridge, and EMIB-T.
The Rio Rancho facility started with 25 people in 1980 and has grown into a state-of-the-art packaging hub with 2,700 employees and over 500 partner companies.
The Foveros process currently in operation at Fab 9 is a method of connecting multiple chiplets with different designs or process nodes to a silicon interposer to form a single high-performance unit.
Intel explained that placing high-power circuits on efficient process nodes can be utilized to extend laptop battery life or miniaturize edge computing devices.
EMIB is a technology that embeds small silicon bridges directly into the substrate for inter-chip connections.
It was reported that cost savings are possible compared to the method of using silicon interposers across the entire area, and multiple chiplets can be interconnected within a single package.
Intel announced plans to expand its package size, which is currently eight times the industry standard, to more than 12 times by 2028.
EMIB-T, which will be unveiled in 2026, is a structure that adds a power supply channel to EMIB, and it is a method of delivering power directly to the chip rather than around the chip.
Intel stated that this has improved the power efficiency and signal routing performance required for the operation of the latest High Bandwidth Memory (HBM).br />
They also explained that by combining chiplets from various suppliers to configure them on large boards, it is possible to flexibly respond to the construction of large-scale AI engines.
“Some customers come to Intel first for advanced packaging,” said Katie Prouty, manager of the Fab 9 Advanced Packaging Facility. “Successfully delivering products to customers will further increase trust in Intel as a foundry.”
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