Stratix 10 FPGAs and SoCs First to be Produced on Intel's 14nm Tri-Gate Process

Altera announced its Stratix 10 FPGA and SoC family, a next-generation high-end PLD family that delivers significant advances in performance, integration, density, and security.

"HyperFlex is the greatest FPGA architectural innovation in the past decade," said Patrick Dorsey, senior director of product marketing at Altera.

The performance delivered by Stratix 10 FPGAs and SoCs is “unprecedented in the industry,” enabling customers to design and innovate in ways never before possible with FPGAs, meeting the demanding needs of next-generation communications, data centers, IoT infrastructure, defense, and high-performance computing systems.

Stratix 10 FPGAs and SoCs are Altera's first products based on Intel's 14nm Tri-Gate process, and utilize Altera's innovative HyperFlex FPGA fabric architecture to double core performance while reducing power consumption by 70% compared to previous-generation FPGAs. This further strengthens Altera's leadership position as the only supplier of high-end SoC FPGAs.

HyperFlex Architecture: Registers Everywhere!

Stratix 10 FPGAs and SoCs are the first Altera devices to adopt the new HyperFlex architecture. HyperFlex architecture doubles core logic performance by introducing registers into all interconnect routing areas of the core, eliminating latency in critical paths and routing.

HyperFlex architecture solves the wiring delay problem of existing architectures.

"Until now, routing delay has been the bottleneck that has held back FPGA performance improvements," said Patrick Dorsey.

The HyperFlex architecture solves this wiring problem by adding a large number of hyper-registers, equivalent to 10 times the number of adaptive logic modules (ALMs), to every wiring area through the concept of "Registers Everywhere," enabling advanced optimization features such as Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization to double the speed.

The addition of numerous hyper-registers enables powerful optimizations.

"HyperFlex not only doubles speed by adding hyper-registers to the wiring, but also reduces board area by 30 percent due to a smaller bus size. It also reduces the required logic area, enabling high-performance designs to operate at up to 70 percent lower power. For example, Stratix 10 can achieve the same performance with half the bus width of Stratix V, so the power required is also significantly reduced by 40% to 70%."

Hyperpipelining using hyper registers provides a 2x speedup.

These advantages make Stratix 10 an ideal solution for data centers where power consumption is emerging as a major challenge.

"Data centers are a new area where FPGAs are starting to be used, and with the Stratix 10, we're adding a hard floating-point DSP, which gives us up to 10 teraflops of speed, so we can replace ASICs or GPUs in the data center," said Patrick Dorsey.

"Of course, Stratix 10 will also see increasing use in other areas such as wireless, military, IoT infrastructure, and high-end broadcast systems," he added.

Altera is focusing on data centers as a new application area for FPGAs.

Scalability and flexibility provided by heterogeneous 3D SiP technology

The Stratix 10 FPGA and SoC family leverages heterogeneous 3D SiP integration technology to efficiently and cost-effectively integrate high-density monolithic FPGA core fabric with other advanced components, enhancing scalability and flexibility.

What makes this possible is Intel's patented Embedded Multi-die Interconnect Bridge (EMIB) technology, which achieves higher performance, reduced complexity, lower cost, and improved signal integrity than interposer-based techniques.

Future FPGA products will support transceivers with various data rates, new modulation schemes, as well as rapidly evolving standards and various protocols.Hey, you have to.

However, since these standards have not yet been established, hard IPs cannot be created. Altera's heterogeneous 3D SiP technology enables it to rapidly deliver a wide range of Stratix 10 device product versions to meet these rapidly changing market demands.

“For example, the first products in the Stratix 10 family currently use this EMIB technology to integrate high-speed serial transceiver and protocol tiles into the monolithic core logic, but in the future, we could also integrate various tiles that provide features such as higher transceiver speeds (56 Gbps), multiport Ethernet, new communication standards like PCIe Gen 4, new modulation formats (PAM-4), analog, or high-bandwidth memory,” explained Patrick Dorsey.

Another power-saving solution: Enpirion PowerSoC

"Altera is no longer just an FPGA company; it's also a power management company," said Patrick Dosey.

Altera's Enpirion PowerSoC power modules for Stratix 10 FPGAs and SoCs meet stringent performance and power requirements, achieving the highest efficiency while providing the smallest footprint.

"For example, Altera's Enpirion EM1130 PowerSoC can achieve dynamic power savings of 20-25%, depending on the application, by introducing SmartVoltage ID (SmartVID) technology, which Intel uses across all its programs, into the Stratix 10."

Maximize design protection with comprehensive security integration.

Altera has achieved world-class security levels through collaboration with partners including Intrinsic-ID, making Stratix 10 FPGAs and SoCs ideal for defense, cloud, and other applications where multi-layered security and isolated IP protection are critical.It is designed to be an ideal solution for applications such as wood security and IoT infrastructure.

A key element that makes Stratix 10 FPGAs and SoCs the industry's most comprehensive and integrated high-performance FPGAs is the innovative Secure Design Manager (SDM), which empowers users to define and build customized, multi-layered security solutions.

SDM provides security features such as sector-based authentication and encryption, multi-factor authentication (MFA), and physically unclonable function (PUF) technology, which makes physical cloning impossible. "For example, PUF technology makes cloning impossible because each device has a unique key determined during the process," added Patrick Dosey.

A comprehensive design environment optimized for HyperFlex

Altera's comprehensive design environment provides a Hyper-Aware design flow optimized for HyperFlex, improving design productivity and accelerating time to market by reducing compile times and design iterations.

The new Spectra-Q engine introduced in Altera's Quartus II design software maximizes the performance, power, and area benefits of the HyperFlex architecture, enabling developers using Stratix 10 FPGAs and SoCs to improve design productivity and accelerate time to market.

Quartus II software reduces compile times by up to 8x and adds new features such as multiple design entry methods, drop-in IP integration, OpenCL support, and a high-level design flow. Developers can immediately begin developing Stratix 10 designs using the Fast Forward Compile performance evaluation tool.

Engineering samples of Stratix 10 FPGAs and SoCs are expected to be available in the fall of 2015. Embedded software developers can accelerate Stratix 10 SoC embedded software development by leveraging the SoC virtual platform provided by Mentor Graphics. For more information about Stratix 10 FPGA and SoC products, contact your local Altera sales office or visit www.altera.com/stratix10.