Bluetooth Smart IC achieves receiver sensitivity of -93 dBm for all channels

Toshiba Corporation has developed a spur-canceled clock generator (SCCG) that restores receiver sensitivity in wireless connectivity ICs.

SCCG restored receiver sensitivity by suppressing spurs, which are interference generated from clock signals, and achieved a receiver sensitivity of -93 dBm for all channels of Bluetooth® Smart ICs.

Toshiba plans to announce this at the VLSI Circuits Symposium 2016, an international semiconductor device conference held in Honolulu, Hawaii, on June 15.



Recent wireless connectivity ICs integrate analog blocks such as RF circuits, mixed-signal blocks such as AD converters, and digital blocks on a single chip. However, some harmonics of the reference clock signal for digital circuits and AD converters, known as clock spurs, degrade receiver sensitivity, and existing sensitivity recovery technologies face issues such as additional power consumption, chip size, and development costs.

Toshiba proposes a clock generator as a solution that suppresses spurts by delaying a portion of the clock. This clock delay generates two types of clock spurts with the same amplitude and reverse phase, which then cancel each other out. Since the clock generator has a power consumption of 18μW and a size of 40μm × 120μm, clock spurs can be suppressed without increasing power consumption or size. This method recovers the 4dB of sensitivity weakened by spurs and is applied to Bluetooth Smart ICs to achieve -93dBm receiver sensitivity.

With the recent proliferation of applications such as wearable devices leading to increased demand for wireless connectivity ICs, Toshiba plans to continue expanding its production lineup of high-performance wireless ICs and launch a Bluetooth Smart IC equipped with SCCG this summer.