Debugging Tips from Intel FPGA Design Software Quartus

When designing an FPGA, you must go through the debugging process to check whether the written program is correct and has no errors.

So how can we make debugging easier and faster? Intel's FPGA design software, a debugging tool for correcting errors in FPGAs, provides a satisfactory answer to this question.

This 'Quartus' includes five debug tools: ▶SignalProbe Incremental Routing ▶In-System Memory Content Editor ▶In-System Sources & Probes ▶SignalTap II embedded logic analyzer ▶Logic Analyzer Interface.

First, SignalProbe Incremental Routing helps you connect specific logic cells to external pins without compiling them entirely, so you can check them with a logic analyzer or oscilloscope. In general, in the case of FPGAs, fitting and routing tasks must be performed together because internal resources are used to connect internal signals to the outside. However, the Incremental Routing function can be performed quickly because it connects to the outside using previously unused routing resources. .

Additionally, the 'In-System Memory Content Editor' is used to check and update the contents of the internal memory via JTAG (Joint Test Action Group). ISMCE can modify or update internal memory while the device is running, and it must be connected because it happens through the JTAG controller. The IPs supported by ISMCE are LPM_CONSTANT, single port ROM and RAM.

'In-System Sources & Probes' also works via JTAG. Each ISSP can have up to 512 probes and toggles during runtime. In simple function debugging, if an instance of ISSP IP is possible, a connection is absolutely necessary because JTAG is used as a debugging channel, and it can be used in a PC environment without additional external devices.

The function of 'SignalTap II embedded logic analyzer' is to monitor internal signals using predefined clock signals. Various signals can be monitored in real time. Add SignalTap II to the completed custom code, select the target probe point, and set the trigger condition. Then compile the entire code and program the result value to the device. The analysis results can be viewed through the debugging GUI of SignalTap II.

Finally, the 'Logic Analyzer interface' is used to increase visibility of signals inside the FPGA. It connects internal signals to I/O pins and then connects them to external test devices. Up to 256 internal signals can be connected to each pin, and internal probe points can be quickly switched and connected. No need to recompile or reconfigure separately for work.

Intel's Axios FAE Vice President Hyunsoo Jeon said, "Intel's 'Quartus' has an intuitive GUI environment for easy user access. The debugging tool also allows debugging of specialized blocks such as transceivers, including basic internal logic." He added, "When using a debugging tool, it is important to secure the JTAG connection and then use the appropriate tool according to the situation."

A detailed explanation of the Intel Quartus debugging tools and how to use them appropriately for each debugging situation can be found in the online webinar (eeWebinar).