Microsemi PolarFire SoC
Royalty-free open RISC-V ISA-based
Microprocessor Subsystem Combination Architecture

With the advent of an era where the convergence of 5G, machine learning, and IoT drives computing, embedded developers require the diverse capabilities of Linux-based operating systems. To meet these requirements, deterministic system requirements must be satisfied in design environments where power and temperature are more limited than ever, as well as critical security and reliability requirements. Traditional SoC FPGAs, which combine reconfigurable hardware and Linux-supported processing capabilities on a single chip, provide devices suitable for customization, but they come with drawbacks such as high power consumption, a lack of proven security and reliability, and a low-flexibility and expensive processing architecture.
To address this, Microchip Technology expanded its Mi-V ecosystem by launching an SoC FPGA architecture that combines the mid-range PolarFire FPGA family with a royalty-free, open RISC-V ISA (Instruction Set Architecture)-based microprocessor subsystem through its subsidiary, Microsemi Corporation.

Microchip’s PolarFire SoC architecture, unveiled at the RISC-V Summit in Santa Clara, California, provides real-time deterministic Asymmetric Multiprocessing (AMP) capabilities to Linux platforms with multicore coherent CPU clusters. Co-developed with SiFive, the PolarFire SoC architecture features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad, or direct access memory. This architecture enables developers to run deterministic real-time embedded applications with various operating systems for various temperature and space-constrained applications in networked cooperative IoT systems.

Bruce Weyer, Vice President of Programmable Solutions at Microchip, said, “The PolarFire SoC architecture supports real-time capabilities in Linux based on a powerful combination of configurable devices, low power, security, and reliability,” adding, “Building on Microchip’s Mi-V RISC-V ecosystem and system solution portfolio, the PolarFire SoC architecture provides customers with a platform to address the next-generation challenges of the computing industry.”

The PolarFire SoC includes extensive debug features such as instruction traces, 50 breakpoints, a passive run-time configurable AXI (Advanced eXtensible Interface) bus monitor, and an FPGA fabric monitor, as well as Microchip's built-in 2-channel logic analyzer, SmartDebug. In addition, the PolarFire SoC architecture is equipped with reliability and security features such as SEC-DED (Single Error Correction and Double Error Detection) for all memory, physical memory protection, DPA (Differential power analysis) Safe Crypto Core, defense-grade Secure Boot, and 128Kb Flash Boot Memory.

"Naveed Sherwami, CEO of SiFive, stated, 'The PolarFire SoC architecture, a fully customizable programmable RISC-V platform, enables developers to design innovative Linux-based SoCs in new and exciting ways according to the unique requirements of specific fields.' He added, 'The PolarFire SoC leverages SiFive's market-leading U54-MC CPU core complex to provide developers with the capability to overcome the overall challenges of building real-time systems through predictable behaviors.'"