Ethernet bandwidth growth trend, FPGA use spreads
FPGAs accelerate Ethernet payload data processing
Quarters Ethernet Toolkit, Design and Debugging Support


As demand for large-scale data transmission grows, Ethernet bandwidth has steadily expanded. However, the proliferation of 5G and IoT, the rise of AR, VR, and 4K content, the rise of cloud computing, and the proliferation of remote work and work-from-home systems are adding to the traffic burden on wired and wireless infrastructure.

One way to implement high-speed Ethernet is to replace the Ethernet controller with an FPGA. FPGAs offer the advantage of allowing performance optimization tailored to the user's needs. However, utilizing them can be challenging without prior FPGA knowledge and experience.

FPGA manufacturers are also aware of the difficulties faced by customers in the field, and are therefore providing various design materials and verification tools for customers who wish to adopt FPGAs instead of Ethernet controllers.

We asked Hyung-Sook Kim, a manager in charge of Intel FPGA technical support at Uniquest, about how to easily implement high-speed Ethernet and how to verify the implemented network.



Q. What are the benefits of adopting FPGAs in high-speed Ethernet implementations?

A. Implementing high-speed Ethernet using an FPGA instead of a commercial Ethernet controller allows the FPGA to handle the Ethernet payload data processing that the host must perform with low latency, reducing the workload on the server CPU.



Q. Among Intel FPGA products, the 'Arria 10' series and 'Stratix 10' series are mainly used for Ethernet implementation. What are the differences between the two?

A. Intel provides both PHY and MAC hard IP for the Stratix 10 series, the higher-end model of the Arria 10 series. In contrast, the Arria 10 series provides only hard IP for the PHY, and only soft IP for the MAC.



Intellectual Property (IP) is a reusable functional block with independent functionality used in circuit design for devices such as SoCs (Systems on Chips) and FPGAs (Field Programmable Gate Arrays). It is typically divided into soft IP, in the form of RTL (Register Transfer Level) code capable of logic synthesis, and hard IP, in the form of design data that has been placed and routed according to a defined process. Hard IP is easier to implement than soft IP.



Q. What are the advantages of implementing the PHY and MAC of high-speed Ethernet with hard IP?

A. Ethernet speed and operating clock are proportional. When the PHY and MAC are implemented as hard IP, they are unaffected by other logic, preventing any fluctuations in the timing of the Ethernet hard IP operating clock. Delay is also lower than when implemented as soft IP. Furthermore, the internal FPGA resources occupied by the soft IP can be used to implement other logic.



Q. What are the features of the transceiver tiles of the Intel Stratix 10 series, such as H-tile, P-tile, and E-tile?

A. H-tile is similar in structure to the transceiver of the Arria 10 series. It supports 28.3G NRZ and implements PCIe gen3 x16 and 50/100G Ethernet MAC as hard IP. P-tile is a PCIe-only transceiver tile with PCIe gen4 x16 implemented as hard IP.

E-tile supports 28.9G NRZ and 57.8G PAM-4, and implements 10/25/100G Ethernet MAC and RS-FEC as hard IP, reducing soft MAC IP costs.



Q. What factors should I typically check to verify normal operation after building a High-Speed Ethernet PHY and MAC?

A. Since the PHY is configured with an Intel FPGA transceiver, the transceiver operation is verified with signals such as △cdr_lock, △rx_block_lock, △tx_pll_locked, △ehip_ready, and △tx_lanes_stable. Next, the Ethernet IP output clock must be verified.



Q. What tools does Intel provide for FPGA-based high-speed Ethernet verification?

A. The Ethernet Toolkit is a free Ethernet debugging tool provided with Intel® Quartus® Prime, and is not available from competitors. The Ethernet Toolkit can be used immediately with just the Intel FPGA Download Cable.



The Ethernet Toolkit allows users to monitor the status of FPGA-based Ethernet connections in real time and access the configuration and status registers of Ethernet IP. More information will be available during the e4ds EE webinar on Tuesday, June 3rd, at 10:30 AM.