SK Telecom is moving to improve the efficiency of its AI data centers (DCs) by fundamentally changing the way computing resources are connected. This decision stems from the assessment that expanding solely by increasing the number of GPUs is insufficient to resolve the issues of rising memory demand and resource utilization imbalances.

SK Telecom announced on March 4 (local time) that it signed a Memorandum of Understanding (MOU) with Pannesia at MWC26 in Barcelona, Spain, for the joint development of a 'CXL-based next-generation AI DC architecture'.

The two companies are pursuing a structural transition based on CXL (Compute eXpress Link) to flexibly connect and combine resources, aiming to reduce inefficiencies arising from the existing architecture where CPUs, GPUs, and memory are fixed at the server level. The plan is to alleviate the limitation where other servers struggle to utilize surplus resources even when one server is empty, and specifically to reduce the need to expand GPU capacity alongside memory when demand increases.

We are also considering a method to selectively utilize necessary resources by extending the scope of resource connectivity beyond the internal server to the rack unit, which groups multiple servers together. The explanation is that the goal is to create a structure that connects the CPU, GPU, and memory more densely by utilizing CXL.

The initiative also included attempts to change the connection path itself. While it was previously common practice to exchange data via general-purpose networks such as Ethernet during GPU collaborative computing, a plan to implement CXL-based connections is being pursued, considering that data copying and software intervention during this process can cause latency.

A division of roles was also presented. SK Telecom will lead the structural design optimized for commercial environments based on its capabilities in building and operating large-scale AI DCs and its experience in developing and commercializing AI models, while Panesia will provide the technical elements necessary to expand the connection structure based on CXL-related link semiconductor technologies, such as fabric link switches and link controllers.

The two companies plan to comprehensively verify GPU and memory utilization, latency, and throughput while running actual AI models, and then unveil the results of the next-generation AI DC structure by the end of 2026. Afterward, they plan to pursue commercialization and business development following large-scale AI DC environment demonstrations.