South Korean fabless company Panesia is accelerating its push into the global data center market by leveraging next-generation AI infrastructure connectivity technology.

Panesia announced on the 16th that it will begin additional production of sample chips for fusion switches that support both PCIe 6.4 and CXL 3.2 in the second half of this year.

The company explained that this product is an ASIC switch that not only incorporates all the core features of the CXL 3.2 standard but also uniquely supports Port-Based Routing (PBR) in the industry.

The key to this chip lies in its ability to flexibly connect different devices within a single network.

According to Panesia, the switch can handle both PCIe and CXL protocols on a single chip, allowing various equipment used in modern data centers and high-performance computing (HPC), such as GPUs, CPUs, memory expansion units, and AI accelerators, to be connected within a single structure.

In particular, it is designed to enable the implementation of a 'composable architecture' at the rack level, which combines resources as needed rather than in a fixed manner, with a focus on reducing resource waste in large-scale AI training and inference environments.

Panesia stated that this structure helps reduce investment and operating costs for systems required for large AI workloads such as LLM, RAG, and DLRM, as well as scientific and technological computing.r />
The most notable differentiating factor is the routing structure.

Typically, data center connectivity structures are often bound by Hierarchical Routing (HBR) that resembles a tree structure, but Panesia has incorporated Port-based Routing as well.

The company explained that using this feature allows for more flexible fabric topology design and improves overall system efficiency by reducing data transfer paths between devices.

They also stated that through the cascading function, which directly connects switches, up to thousands of devices across multiple server racks can be bundled into a single fabric.

This means that communication between devices can be handled without relying heavily on external networks, which aligns with the goal of reducing bottlenecks in large-scale AI infrastructure.

In terms of performance, it also aimed for high bandwidth and low latency simultaneously.

Panesia stated that it supports all major CXL sub-protocols, such as CXL.cache, CXL.mem, and CXL.io, enabling consistency across devices.

The product introduction page states that this switch features a 256-lane-based go-fan-out structure and latency characteristics of less than 100 nanoseconds, and is designed based on the company's low-latency CXL IP.

Panesia believes that this can boost communication efficiency between devices in large-scale AI and HPC environments.

Panesia is a company that has recently been rapidly expanding its presence in the CXL sector.

The company unveiled a fabric switch and pilot system of the same family at CES 2026 earlier this year, and at that time, it also highlighted support for CXL 3.2 features, including PBR.

It was also mentioned that the company raised approximately 80 billion won during the Series A investment round in 2024 and was valued at around 340 billion won..