The Era of 1 Million GPUs: Bottlenecks Are 'Wiring,' Not Computation… CPOs Are Changing the Data Center Landscape
Published2026.07.31 12:04AI data centers face data movement as a bottleneck rather than GPU computation. CPO (Co-Packaged Optics), which packages switch ASICs and optical engines together, is emerging as a key technology to reduce copper wiring limitations and address power and latency issues.
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Professor Im Seung-chan, “Areas that humans, not ‘analog’ AI, must continue to handle and resolve”
To use LTspice, one of the analog circuit design tools, effectively, an intuitive understanding of analog circuits is required beyond basic usage. In this context, e4ds news has prepared education where designers can develop their design sense by simulating practical circuits such as amplifiers, filters, switching power supplies, and ADCs, and strengthen practical capabilities through examples connected to industrial sites such as flyback converters. Accordingly, we met with Professor Lim Seung-chan, who will be in charge of this training, to learn about the lecture content as well as the continued importance of analog technology and the value of engineer collaboration.
2026.04.28by 배종인 기자
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The Future of AI Data Centers, Why CPO Now?… e4ds EEWebinar to be held on July 21
e4ds news will host a webinar on July 21st through the e4ds EEWebinar titled 'Why CPO Now? The Future of Data Center Optical Interconnects'. Advisor Im Seung-chan, who will present at this webinar, plans to introduce the technical limitations faced by data centers in the AI era and the development direction of next-generation optical interconnect technology.
2026.07.08by 배종인 기자
ASML, TSMC, and Samsung Play the '12-inch Photomask' Card…40-Year Semiconductor Standard Changes
ASML, TSMC, Samsung Electronics, and Intel have begun a joint industry standard transition in the era of High NA EUV, now pointing in the same direction. On the surface, this appears to be an announcement related to High NA EUV (extreme ultraviolet), the next-generation lithography equipment, but the essence of this move is not equipment adoption. It is an industry transformation project that changes the photomask specifications themselves, one of the core infrastructures of semiconductor production.
2026.09.09by 배종인 기자
TSMC·ASML Promote Transition to 12-inch Photomasks for High NA EUV...Target Mass Production in 2033
TSMC and ASML announced on the 8th that they have launched a joint industry initiative for transitioning to 12-inch photomasks for High NA EUV. The two companies aim to establish a 12-inch photomask pilot line in 2031 and apply the related exposure system to mass production of advanced processes by 2033.
2026.09.09by 배종인 기자
Intel Foundry and ASML Achieve Breakthrough in High NA EUV Application to Over 1 Million Wafer Processes
Intel Foundry and ASML have disclosed their mass production achievements with High NA EUV lithography technology. To date, High NA EUV has been applied to over 1 million wafer processes, and is currently being utilized in mass production of certain layers of Panther Lake processors. The two companies are strengthening industry cooperation for near-term support based on 6-inch masks and future transition to 6×12-inch masks.
2026.09.08by 배종인 기자
