Realizing data acceleration with the first 7nm NoC technology.

Xilinx, which can be considered the first pioneer of traditional FPGAs, is making unusual moves.

Xilinx's FPGA business, which began as an emulator for semiconductor ASICs, has challenged the CPU and GPU markets, previously dominated by established powerhouses, with a platform that leverages adaptive acceleration technology.

Applications that require fast processing, such as AI, machine learning, and big data processing, require fast server-side processing and efficient utilization of computing resources. For this reason, FPGAs have been widely used in data center servers to help accelerate CPUs and GPUs, and Intel's acquisition of Altera is also being used to accelerate CPUs in existing X86 servers.

Since its 2016 announcement targeting hyperscale data centers, Xilinx has been working with large internet service providers like Google, Microsoft, and Amazon to deliver its FPGA-powered acceleration stack for cloud applications, reVision , which has demonstrated up to 6x faster machine learning inference and 40x faster computer vision processing than competing GPUs.
Built after four years of development, 1,500 engineers, and $1 billion in research and development, this ACAP represents a new approach to data center business.

Rather than simply providing acceleration support, the product itself can function as a CPU or GPU, and at times, it can also act as a simple acceleration support, approaching it as a flexible, independent, adaptable acceleration platform. This is possible thanks to the continued development of 3D IC stacking technology that enables continuous programmable cores and other IC integration technologies and fast data rates, said CEO Victor Peng.

The next-generation programmable logic, aka 'Everest' FPGA, consisting of 50 billion transistors through 7nm, which may be the last of Moore's Law, shows a workload that is 10 to 100 times faster than the processing speed of existing CPUs, and in the field of DNN (Deep Neural Networks) applications, it provides more than 20 times higher performance than the existing 16nm Virtex VU9P.

Additionally, the official said, "In the AI field, it can provide 40x inference speed, 90x analysis speed, and 100x genome speed-up, and this product experience will be activated through ACAP use by FaaS service providers using FPGAs in cloud infrastructure."
The 5G remote radio head is expected to support four times the bandwidth of the current 16nm UltraScale+ RFSoC family, delivering breakthrough efficiency for remote radio heads for massive-MIMO, millimeter-wave mobile backhaul, 5G baseband, fixed wireless access, remote-PHY nodes for cable, electronic warfare/radar, test and measurement, SATCOM, Milcom/Airborne radio, and other high-performance RF applications..
The ACAP portfolio announced by Xilinx this time is manufactured using TSMC's 7nm manufacturing process, and tape out, the final stage of integrated circuit design, is scheduled for the end of this year, in December 2018.
Xilinx announced that it invested a total of four years of development, 1,500 engineers, and over $1 billion in R&D costs for this ACAP-based project, Everest. Regarding the disclosure of these figures in particular, Ahn Heung-sik, CEO of Xilinx Korea, stated that it shows a significant business transformation and Xilinx's direction for the next five years, and that ACAP will be applied to expanding business areas centered on data centers, as well as existing automotive, 5G, audio and video, aerospace, and instrumentation fields, as well as encryption technology, which is a recent trend.
Xilinx hasn't disclosed exactly what the 50 billion transistor Everest will be, but it's likely to be a mix of bare-die monolithic and interposer designs.

The ACAP block diagram, which boasts faster communication speeds than existing products, ensures high-speed data rates by applying the first NoC (Network on Chip) high-speed communication fabric at 7nm. This is in line with one of the three big trends identified by CEO Victor Peng: that hardware must be as agile as software.
NoC (Network on Chip) connects Xilinx's high-performance next-generation programmable logic, application processors, real-time processors, programmable engines, RF, high-speed SerDes, programmable IO, and HBM at high speed, as shown in the block diagram. Additionally, the core idea of the adaptive acceleration platform, optimized computation and adaptability, is operated in a structure that leaves programmable silicon through dedicated hard block space of the FPGA.
In response to our question, "Is ACAP targeting both the CPU and GPU markets?", Xilinx's CEO, Ahn Heung-sik, said, "While CPUs and GPUs maintain their general-purpose operation fields, the ACAP platform has a flexible structure that allows for automatic adaptation of performance acceleration functions," adding, "This structure will be appropriate for fields requiring high-difficulty, high-speed multi-tasking."

By mentioning representative fields such as video transcoding, database operations, data compression, search, inference through AI, genomics, machine vision, computational storage, and network acceleration, it was indicated that ACAP aims to establish itself as a category of general-purpose accelerator in the market.
In this ACAP announcement, Victor Peng cited data centers as the segment with the greatest growth potential, stating that Xilinx's ACAP platform will enable rapid upgrades, faster customer requirements, and rapid evolution of the product portfolio.

Xilinx is currently shipping software for ACAP testing to key customers, with the design expected to be finalized by the end of 2018 and shipping in mid-2019.